半导体工艺技术--43张课件

半导体工艺技术,第十三章 前瞻性工艺研究,*,单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,*,新型器件结构,目前研发焦点,“无光源”纳米结构制备技术,1,新型器件结构1,1900,1950,1960,1970,2000,Vacuum,Tube,Transistor,IC,LSI,ULSI,10,cm,cm,mm,10,m,m,100,nm,一百年中，电子开关器件的关键（最小）尺寸缩小10,6,倍!,10,-1,m,10,-2,m,10,-3,m,10,-5,m,10,-7,m,器件几何尺寸的持续减小成就了微电子技术的无处不在，产生了无数的应用，造就了信息社会。,Down Scaling,：,Enabler,2,19001950196019702000VacuumTran,器件几何尺寸的减小直接导致,：,1、减小寄生电容，由此减小MOSFET的开关时间,减小功耗,2、增加单位面积晶体管的数量,增强电路功能,促成并行运算,增大运算速度,器件几何尺寸的减小最为关键、有效,Prof. Iwai, Tokyo Inst Tech.,为什么要减小器件的几何尺寸,?,3,器件几何尺寸的减小直接导致：器件几何尺寸的减小最为关键、有效,集成电路特性的改善和成本的降低主要是通过晶体管几何尺寸持续不断地减小得以实现的。,集成电路工艺的发展和进步,Performance / Cost,Market Growth,ITRS，International Technology,Roadmap for Semiconductors,Transistor Scaling,PITCH,Investment,YEAR:,2019,2019,2019,2019,2019,HALF-PITCH:,65 nm,45 nm,32 nm,22 nm,15 nm,4,集成电路特性的改善和成本的降低主要是通过晶体管几何尺寸持续不,Wakabayashi,NEC,Length of 18 Si atoms,It,s real (nano-device)!,5,WakabayashiLength of 18 Si ato,体硅MOSFET技术,Current flowing between the Source and Drain is controlled by the voltage on the Gate electrode,Substrate,Gate,Source,Drain,M,etal-,O,xide-,S,emiconductor,F,ield-,E,ffect,T,ransistor:,栅长,L,g,绝缘氧栅厚度,T,ox,结深,X,j,M. Bohr,Intel Developer,Forum, September 2019,G,S,D,courtesy of Prof. Kuroda,Keio University),期望得到的MOSFET特性,:,开启时驱动电流要大（,High ON current）,关闭时漏电流要小,（Low OFF current）,|GATE VOLTAGE|,CURRENT,V,T,6,体硅MOSFET技术Current flowing betw,MOSFET,：一个低功耗、效率高的逻辑开关,P well,n,+,source,n,+,drain,Gate oxide,n,+,poly,gate,Gate spacer,V,G,Log(I,D,),Ideal switch,V,t,I,on,I,off,MOSFET switch,I,off,L,W,S/C,W,D/C,Source,Drain,V,G,=V,D,Channel,BC,P,V,D,-,-,-,-,-,-,-,-,-,-,-,-,N,+,N,+,N,+,-,-,-,-,L,W,S/C,W,D/C,Source,Drain,V,G,=0,Channel,BC,P,d,-,-,-,-,-,-,-,-,-,-,-,-,N,+,N,+,N,+,After,F,.,B,OE,UF, MIGAS 2019,7,MOSFET：一个低功耗、效率高的逻辑开关P welln+,为什么需要新的晶体管结构?,当沟道长度,L,g,减小时，漏电流必须得到有效的控制,漏电流同时也发生在远离沟道的表面区,Lets get rid of it!,Drain,Source,Gate,Thin-Body,MOSFET,Buried Oxide,Source,Drain,Gate,Substrate,“Silicon-on-Insulator” (SOI),Wafer,L,g,8,为什么需要新的晶体管结构?当沟道长度Lg 减小时，漏电流必须,薄体MOSFET,使用薄体可以有效地控制漏电流，要求：,T,Si,L,g,双栅结构更有利于沟道的缩短，可至,L,g,10 nm,Ultra-Thin Body (UTB),Buried Oxide,Substrate,Source,Drain,Gate,T,Si,L,g,Double-Gate (DG),Gate,Source,Drain,Gate,T,Si,9,薄体MOSFET使用薄体可以有效地控制漏电流，要求：TSi,双栅 “FinFET”,Planar DG-FET,Gate,Source,Drain,Gate,T,Si,Fin Width =,T,Si,L,g,GATE,SOURCE,DRAIN,20 nm,10 nm,Y.-K. Choi,et al,.,IEEE Intl,Electron Devices Meeting,2019,15 nm,L,g,FinFET:,Fin Height,H,FIN,=,W,/2,D. Hisamoto,et al., IEEE Intl Electron Devices Meeting, 2019,N. Lindert,et al,.,IEEE Electron Device Letters, p.487, 2019,FinFET,Source,Drain,Gate,L,g,10,双栅 “FinFET”Planar DG-FETGateSo,14 nm,10 nm,A,B,Metal,Gate,Nanowire,Channel,Metallic,Source,Metallic,Drain,High-K gate,dielectric,Spacer,Spacer,A,B,L,G,10 nm,d 14 nm,d 10 nm,一种可能的未来MOSFET的结构,11, 14 nmABMetalNanowireMetalli,目前研发焦点:,如何增大驱动电流？,Courtesy,Prof. Saraswat (Stanford University),Low S/D resistance,12,目前研发焦点: 如何增大驱动电流？Courtesy Pro,前端工艺中的一些关键技术,原子层级淀积 Atomic layer deposition (ALD),实现栅氧层淀积的原子层级控制,脉冲激光退火 Pulsed laser annealing,实现超快、低“热预算”（即小,Dt,）高温退火,等离子浸没式注入 Plasma immersion implantation,实现超浅离子注入,高电导沟导工程 High mobility channel,实现局域压缩或拉伸应力,等等,Prof. Iwai, Tokyo Inst Tech.,13,前端工艺中的一些关键技术原子层级淀积 Atomic laye,后端工艺中的一些关键技术,Prof. Iwai, Tokyo Inst Tech.,原子层级淀积 Atomic layer deposition (ALD),实现铜籽晶层和扩散阻挡层淀积的原子层级控制,多孔金属间介质薄膜的材料和工艺,有效地减小互连体系中的寄生电容,大马士革工艺 Damascene processing,实现取代传统铝布线的先进铜互连技术,三维多层金属布线 Multilevel-multilayer metallization，3D,有效使用珍贵的硅表面，实现超大规模集成技术,等等,14,后端工艺中的一些关键技术Prof. Iwai, Tokyo,G,raphene sheet,S,ingle-walled carbon nanotube (SWNT),Various kinds of semiconducting nanowires:,Si, Ge, InSb, GaAs, SiC, GaN, ZnO, etc.,15,Graphene sheetSingle-walled ca,关键尺寸, 100 nm,Resist,Courtesy Per-Erik Hellstr,m（Hellberg）,“无光源”纳米结构制备技术,16,关键尺寸 100 nmResistCourtesy Pe,Ref：KLA,Tencor,Wave length (I),Line width,Deep Sub-wavelength Litho,Sub-wavelength Litho,OPC at,180 nm,Aggressive OPC,at 30%,for each node,Immersion,Lithography,350 nm,365 nm,180 nm,248 nm,193 nm,130 nm,90 nm,65 nm,45 nm,PROCESS CONTROL: THE INVESTMENT THAT YIELDS,Novel Processing（工艺革新）,：Enabler,Prof. Iwai, Tokyo Inst Tech.,17,Ref：KLA TencorWave length (I)D,为什么“光刻”技术如此成功,?,价格方面：,193 nm,光刻设备, 20 M$,一套光刻版, 1 M$,高分辨率并能实现大批量生产！,100 wafers/hour,18,为什么“光刻”技术如此成功?价格方面： 193 nm 光,光刻基本要求,理想的光刻,分辨率,Resolution,Good,图形,Pattern shape,Any,大、小图形混合,Large & small patterns,Yes,对准精度,Alignment,Good,产量,Throughput,High,初始价位,Initial cost,Low,运行费,Running cost,Low,19,光刻基本要求 理想的光刻分辨率ResolutionGood图,适用于小批量制备,/,制造的纳米级“光刻”,电子束曝光，,EBL,：,Electron-Beam Litho,纳米压印，,NIL,：,Nano-Imprint Litho,“侧墙转移”，,STL,：,Sidewall-Transfer Litho,20,适用于小批量制备/制造的纳米级“光刻”20,EBL,的特征和优点,直写、灵活,任意形状,0.1 nm,束斑直径,/,宽,5 nm,21,EBL的特征和优点直写、灵活21,EBL,的分辨率,高能：,100 keV,高对比度的光刻胶,薄,光刻胶,用叠层光刻胶,用“硬胶”,Hard mask,Wafer,Thick resist,Thin resist,Wafer,Hard Mask,22,EBL的分辨率 高能：100 keVWaferThick r,EBL,分辨率的提高,使用不同光刻胶的对比,相等亮,/,暗线宽的分辨率,23,EBL分辨率的提高 使用不同光刻胶的对比23,NIL,工艺流程和特征,压印及,UV,光辐照,Step and flash,分辨率,10 nm,任意图形,石英母版复制实用版方法,套刻精度,1 m，有声称到 100 nm的,C.R.K. Marrian and D.M. Tennant, JVST, 2019,50 nm pillars after 500 imprints with the same master,24,NIL工艺流程和特征压印及UV光辐照 Step and fl,NIL,在大尺寸硅片上应用实例,25,NIL在大尺寸硅片上应用实例25,NIL,在多栅纳米晶体管,FinFET,中应用实例,26,NIL在多栅纳米晶体管FinFET中应用实例26,NIL制作的互连双大马士革结构。减少制作步骤。,27,NIL制作的互连双大马士革结构。减少制作步骤。27,Top view,Cross section,Wafer,SiO,2,poly-Si,Si,0.2,Ge,0.8,Resist,“侧墙转移”,STL,的工艺流程，,1,目标：制备纳米级多晶硅栅（红色条块）,28,Top viewCross sectionWaferSiO2,Top view,Cross section,Wafer,SiO,2,poly-Si,Si,0.2,Ge,0.8,SiN,STL,的工艺流程，,2,29,Top viewCross sectionWaferSiO2,Top view,Cross section,Wafer,SiO,2,poly-Si,Si,0.2,Ge,0.8,SiN,SiN,STL,的工艺流程，,3,30,Top viewCross sectionWaferSiO2,Top view,Cross section,Wafer,SiO,2,poly-Si,SiN,Resist,STL,的工艺流程，,4,31,Top viewCross sectionWaferSiO2,Top view,Cross section,Wafer,SiO,2,poly-Si,SiN,Resist,STL,的工艺流程，,5,32,Top viewCross sectionWaferSiO2,Top view,Cross section,Wafer,SiO,2,poly-Si,SiN,Resist,STL,的工艺流程，,6,33,Top viewCross sectionWaferSiO2,Top view,Cross section,Wafer,SiO,2,poly-Si,STL,的工艺流程，,7,SiN,34,Top viewCross sectionWaferSiO2,10 poly-Si lines,Width=45 nm,poly-Si contact,H=15 nm,W=15 nm,poly-Si,NiSi,50nm,150nm,Si,STL,的工艺流程，,8,35,10 poly-Si linespoly-Si contac,Fin W=35 nm,Fin H=27 nm,L=70 nm,Zhang & Qiu,et al.,IEEE EDL May 2019,Al wiring,Contact holes to S/D,Double Fin channel,Gate,FinFET produced using STL twice,36,Fin W=35 nm Zhang & Qiu et al.,常规光刻技术和标准硅薄膜工艺技术的革新和结合,对细线条而言，理论上,k,1,0,Pitch,的大小由,常规光刻技术的分辨率决定,常规光刻技术,的使用保证了高产率,“侧墙转移”,(,STL),的特征和优点,37,常规光刻技术和标准硅薄膜工艺技术的革新和结合“侧墙转移”(,2,n,lines after n iterations of spacer lithography!,1st Spacers,2nd Spacers,3rd Spacers,运用STL技术产生高密度图形,Photo-lithographically,defined,sacrificial structures,Y.-K. Choi,et al,.,JVST-B,21, 2951-2955 (2019),38,2n lines after n iterations of,STL工艺中线条尺寸的控制,CVD技术淀积的薄膜具有超常均匀性和可控性,STL纳米线的线宽由SiN薄膜决定,STL纳米线的线厚由poly-Si薄膜决定,Choi,et al.,IEEE T-ED,49,436（2019）,L,g,L,g,STL技术得到的栅,均匀的,L,g,通常光刻技术,制备的栅, 不均匀的,L,g,39,STL工艺中线条尺寸的控制CVD技术淀积的薄膜具有超常均匀性,STL,EB,ArF,Kaneko et. al., IEDM2019,用,STL,制备线条的线宽不均匀性非常小,!,STL,40,STLEBArFKaneko et. al., IEDM20,Summary,Ideal,Optical,EBL,NIL,STL,Resolution,Good,Good,Good,Good,Good,Pattern shape,Any,Any,Any,Any,Lines/,Rings,Large&small patterns,Yes,Yes,No,Yes,Yes,Alignment,Good,Good,Good,Poor,Good,Throughput,High,High,Low,Medium,High,Initial cost,Low,High,Medium,Low,Low,Running cost,Low,High,Low,Medium,Low,41,Summary Ideal OpticalEBLNILSTL,半导体工艺技术-43张课件,半导体工艺技术-43张课件,