smic13_icc_flow_allen-课件

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,*,SMIC13 ICC Flow Introduction to Developers,Allen.YangXmart,The IC design backend training item list,IC compiler training overview,ICC and P&R flow overview,PV tool calibre overview,PV DRC/LVS flow overview,STA PrimeTime overview,StarRCXT tool overview,IC,Compiler is an integral part of the Synopsys Galaxy Implementation Platform that delivers a comprehensive design solution, including,synthesis, physical implementation, low-power design,and,design for manufacturability,.,IC,Compiler is a single, convergent, chip-level physical implementation tool that includes flat and hierarchical design planning, placement and optimization, clock tree synthesis, routing, manufacturability, and low-power capabilities that enable designers to implement todays high-performance, complex designs on schedule.,IC Compiler overview,Comprehensive Place and Route System,Multicore support for higher throughput for designs in mainstream silicon technologies,High performance for advanced silicon technologies,Comprehensive optimization capabilities meet timing, area, power, signal integrity, routability and manufacturing objectives,Predictability during the implementation process,Single timer,Complete netlist-to-GDSII solution for best QoR and TTR,ICC advanced features,The typical flow of the IC design and,Physical implementation,The IC design Roadmap,SYNOPSYS flow tools,Usage map,The Partition flow,In Cadence tools,The general flow of ICC P&R,Data setup,floorplanning,placement,CTS,Routing,Chip Finishing/Export,Netlist SDC UPF techfile .db,Setup the Virable,Target_library Link_library,Refrence_library,and create the Milkyway library, read in the verilog netlist and link the design with,the .db,Load the UPF after the netlist read,Create_mw_lib,Read_verilog,Load_upf,Link -force,Set_min_library,Set_operating_conditions,Set_tlu_plus_files,Check_mv_design,The general flow of ICC floorplan,Data setup,floorplanning,placement,CTS,Routing,Chip Finishing/Export,Netlist SDC UPF techfile .db,Create_floorplan,Then for groups,Create_plan_groups,Create_fp_plan_group_padding,Create_fp_placement,Shape_fp_blocks,Commit_fp_plan_groups,Create_power_straps,Add_tap_cell_array,If LOW_POWER enabled then,Create_voltage_area,Add_power_switch,Derive_pg_connection,Preroute_standard_cells,The general flow of ICC place_opt,Data setup,floorplanning,placement,CTS,Routing,Chip Finishing/Export,Netlist SDC UPF techfile .db,Source $SDC,Set_host_options max_cores 6,Place_opt -effort high congestion power area_recovery,Psynopt -area_recovery power -congestion,The general flow of ICC CTS,Data setup,floorplanning,placement,CTS,Routing,Chip Finishing/Export,Netlist SDC UPF techfile .db,Remove_clock_tree,Set_delay_calculation,Define_routing_rule,Set_clock_tree_reference,Set_clock_tree_options,Set_ignored_layer max Metal6,Clock_opt -only_cts -no_clock_route,Set_propagated_clock get_clocks *,Extract_rc -estimate,Psynopt congestion area_recovery,The general flow of ICC Route,Data setup,floorplanning,placement,CTS,Routing,Chip Finishing/Export,Netlist SDC UPF techfile .db,Set_si_options,Set_route_mode_options,Set_route_zrt_detail_options,Source $antenna_rule,Route_zrt_group -all_clock_nets,Extact_rc,Route_opt effort high xtalk power,Insert_zrt_redundant_vias,Insert_stdcell_filler,Verify_zrt_route,Route_zrt_eco,The general flow of ICC export,Data setup,floorplanning,placement,CTS,Routing,Chip Finishing/Export,Netlist SDC UPF techfile .db,Change_names rules verilog -hier,Write_verilog,Set_write_stream_options,Write_stream,ICC floorplan method,ICC,Encounter,DEF,The DEF exchange flooplan and Preroute information only, save time for Edit Power, less iteration there between tools,Solve the discrepancy between ICC and encounter,When we start the place_opt in ICC_shell, we need add the command below here , this command force the preroute to be dont touch ,set_attribute ,get_net_shape -f “route_type = signal_route route_type user_enter,PhysicalVerification tools of Calibre,Calibres physical verification capabilities are the industry standard for accuracy, reliability, and performance.,Calibre nmDRC,and,Calibre nmLVS,are the market share leaders in physical verification.,Calibre also leads the market with innovative features such as incremental DRC, which ensures you can complete your design rule checking quickly and efficiently, and equation-based design rules, which let designers define continuous, three-dimensional functions that accurately and precisely reflect the complex physical interactions of todays nanometer designs.,Layout verification after ICC,The LVS calibre flow introduction,The DRC calibre flow introduction,The output from ICC after chip finish,DRC runset example,command,：,calibre -drc -hier runset,2024/9/29,20,Calibre LVS runset example,v2lvs -v MY_CHIP_LVS.v -l tsmc18_lvs.v -o MY_CHIP_PAD.spi -s tsmc18_lvs.spi,V2lvs,transfer Netlist,to Spice Netlist,calibre -lvs -spice layout.spi -hier -auto RUNSET,2024/9/29,21,PrimeTime overview,The Synopsys PrimeTime suite includes PrimeTime, PrimeTime SI, PrimeTime PX and PrimeTime VX.,Anchored by the most trusted and advanced static timing signoff solution for gate-level designs, the PrimeTime suite offers comprehensive signal integrity analysis, statistical timing analysis and full chip power analysis in a single integrated environment.,Key benefits of PrimeTime,HSPICE-Accurate Results Minimize Over-Design,Integrated Design Environment Improves Productivity,Fast Turn-around Time Speeds Analysis and Signoff,High Capacity Approach Reduces Hardware Costs,Complete Solution Ensures Comprehensive Signoff,PrimeTime STA flow use .sdf,PrimeTime ECO flow,SNPS StarRC tool overview,StarRC is the EDA industrys gold standard for parasitic extraction. A key component of Synopsys Galaxy Implementation Platform, it provides a silicon-accurate and high-performance extraction solution for SoC, custom digital, analog/ mixed-signal (AMS) and memory IC designs.,StarRC is modeling of advanced physical needed for leading-edge process technologies, including 20-nm, 14-nm and beyond. Its seamless integration with industry standard digital and custom implementation systems, timing, signal integrity, power, physical verification and circuit simulation flows delivers unmatched ease-of-use and productivity to speed design closure and signoff verification.,StarRC tools benefits,Foundry gold standard for extraction accuracy with broadest qualification and adoption,Leader in 20-nm and below process modeling, including most trusted foundry source for state-of-the-art FinFET modeling,High performance and capacity for gate and transistor-level extraction, including multi-core and simultaneous multi-corner extraction,Unified 3D fast field solver for critical net, IP, and custom circuit extraction,3D-IC extraction solution for interposer and stacked die,technologies Integration,with PrimeTime timing signoff, IC Compiler physical implementation,The chart flow of RCXT between tools,Tool usage and labs,icc_shell gui,-printvar *drc*,- help *place*,- man create_fp_placement,pt_shell,-restore_session sess10,-printvar *time*,- echo $link_library,Tool usage and labs (1),calibre rve,c,v2lvs i s o v,v2lvs help,