MB主板上电过程

按一下以編輯母片標題樣式,按一下以編輯母片,第二層,第三層,第四層,第五層,*,MB,主板上電過程,前言,電腦的開機只需要對著,Power,鍵輕輕一按即可,.,可這一按具體是如何使電腦能開機工作的呢,?,它的整個過程是怎樣的,?,以下分幾個部分做講解,Content,開機上電動作圖解,主板的電壓定義,主板,的主要開機,信號,介紹,主板開機上電過程（波形和電路）,PWRBTN,Slp-s3(+),Pson,#(-),+5v,+3v,+12v/-12v,+5v,+3v,Power ok,NB_ RESET,Reset,SB,NB,CPU,POWER,SUPER I/O,OR AS016,Cpu,rst,Intel chipset power on sequence,Pwr,ok,Power Sequence,MB Power Sequence,主板基本電壓,(電源控制,IC),POWER,Specification,+12V,11.4 12.6V,-12V,-10.8 13.2V,+5V,4.75 5.25V,+3.3V,3.14 3.47V,+5VSB,4.75 5.25V,主板基本電壓有,5,個，其他電壓都是由這,5,個基本電壓轉換而得,.,主板基本電壓,Item,Global,States,Sleeping,States,Detail description,1,G0,S0,電腦的正常工作狀態,-,作業系統和應用程式都在執行,2,G1,S1,最耗電的睡眠模式,所有原件均有保持電源，除了一些沒有被,使用的,device.,S3,Suspend to RAM,，只有,memory,是唯一有電源供給的原,件,XP,系統下叫做“待機,(Standby)”, Vista,叫做“睡眠,(,Sleep)”.,S4,Suspend to HDD,，在,Windows,中叫休眠,(,Hibernation,）,所,有主記憶體儲器的內容被儲存在硬碟中，從,S4,恢復後，使用,者可以恢復到原本的工作狀態,.,3,G2,S5,Soft off,，只有,standby power,存在,.,4,G3,Battery,Mechanical Off,，,Power cord,被拔掉，只有,Battery.,ACPI,的,Global States,分四個狀態,G0G1G2G3,ACPI,表示高級配置和電源管理介面對於,Windows2000,，,ACPI,定義了,Windows,、,BIOS,和系統硬體之間的新型工作介面。這些新介面包括,Windows,控制電源管理和設備配置的機制。,主板基本電壓,狀態電壓種類有,3,種,1.Main power: S0/S1,2.Dual power:S0/S1/S3,3.Standby power:S0/S1/S3/S4/S5,詳細參考附件：,Main Power,Main power,的產生由,SLP,_S,3,#,去控制,。,按,Power Button,PWRBTN,#,拉,low,通知,SIO,SIO,告知,NB,NB,送出,SLP_S3,#(,此時,SLP_S3,#,為高電平,),PSON#,被拉,low,Power Supply,產生,Main Power,.,Power-up (Main Power),CH1:+12V,Ch2:+5V,Ch3:+3V,Main power (+12V,+5V,+3V) almost ramp up at the same time.,The main power ramp behavior depends on the power supply design.,Standby Power,1,， 在,MB,上，,power supply,只提供+5,VSB,一種,standby,電壓,其他,standby power,都由它轉出來的。,2，,Standby power,上電,(,插上,power cord),主板就會有，但其提供的電流有限。,Dual Power,Dual power,由,standby power,和,main,power,提供，他存在於,S0,S1,S3,這幾種狀態下，由,Gate,信號去控制哪一個,power,輸出。,主板信號簡介,RTCRST#,RSMRST#,PWRBTN,#,SLP_S3#,PS_ON#,PWROK,PLTRST#,RTCRST#,Battery,3.0V,BATT,2.6V,G3,State,BATT comes from BATTERY at G3 state. So BATT will be 2.6V at G3 state.,BATT comes from +3VSB at S5 state. So BATT will be 2.9V at,S5,state.,S5,State,2.9V,RTCRST#,有效,:,在,G3,狀態時,拔掉,battery,此時,SB,收到低電平,會清掉,COMS,內容,;,若要給主板維持時間或,CMOS,內容, RTCRST,信號需要是高電平,.,+3VSB,S5 State,+5VSB,RSMRST,After plugging power cord, +5VSB ramps up.,+3VSB is regulated from +5VSB.,32ms after +3VSB ramps above V,TRIP,(2.2V), RSMRST asserts.,RSMRST will re-assert after,AC power loss, which acts like a wake up event of SB and causes the de-assertion of SLP_S3# to turn on the system.,RSMRST#,Resume reset active,表示所有的,standby power,都,OK,.,RSMRST#:,Resume Well,Reset, this,signal is used for resetting the resume power plane logic.,AUXOK Logic Example:,Let V,PQ3.1,ramps up slower than +3VSB. It is to meet the spec that RSMRST(AUXOK) needs to ramp up after,VTR,is ready with a,delay,(20ms for SB600).,To precisely estimate the resulting delay from +3VSB to AUXOK, we need to implement the RC charge formula.,V,C,If VCC=3.3V, assuming 20ms is needed:,t=RC=20ms, V,C,(20ms)=2.08V, VC(18.63ms)=,2,V,If VCC=5V, assuming 20ms is needed:,2. t=RC=20ms, V,C,(20ms)=,3.16,V, VC(10.22ms)=,2,V,RC is chosen by substituting,V,C,(t,), V,CC, t and solve for RC.,RSMRST#,PWRBTN,#,PWRBTN,#,:,Power Button,#:,代表低電平有效,PWRBTN,#,Pin6 and pin8 is connected to the power button on the chassis.,Pressing power button generate a low pulse to SB and SIO.,Power button can be programmed to generate suspend, hibernate or shut-down event.,Generally PWRBTN# of SB is internal pulled high, R1336 is reserved to avoid internal pull-high malfunction. This must be pulled to standby power.,5. CB918 must be installed: 1.,Debounce, 2. Prevent ESD from directly,going into SB and SIO. 1000PF is a commonly used value.,6. To achieve better ESD resist performance, CB918 should be placed near front panel header.,SLP_S3#,SLP_S3#:,Sleep Control,SLP_S3# is for power plane control. This signal shuts off power to all non-critical systems when in S3(Suspend to RAM),S4(Suspend to Disk), or S5 states.,SLP_S3#,PWRBTN,#,SLP_S5#,SLP_S3#,PS_ON#,S0 State,Press Power Button,In Intel platform, SLP_S3# is always used to turn on the power supply.,When resuming from S3/S4, any wake up event will cause the de-assertion of SLP_S3#,SLP_S5#, and the rest of the power-up power sequence is the same with those resuming from S5.,Some SIO, ex:SMSC5127, uses inverted SLP_S3# to generate,nPS_ON,#.,In SIS platform, PS_ON# is generated from SB itself (,ex:SIS,968).,+12V,+5V,+3V,ATX POWER,S0,S1,S3,S4,S5,SLP_S3#,H,H,L,L,L,SLP_S4#,H,H,H,L,L,SLP_S5#,H,H,H,H,L,SLP_S4#,PSON#,PSON#,是低有效信號,當此信號,為,Low,時,Power Supply,送出,+3.3V,+5V,-5V,+12V,-12V,等電壓,.,而當此信號被拉,High,時,Power Supply,停止送出上面的電壓,.,利用此信號可以設計“,Soft Power down”,的關機功能,.,當使用者對作業系統下關機命令時,.,作業系統亦可關閉所有的應用程式並利用此腳的功能達到自動關機的動作,.,灰色,: +5V Power OK signal,綠色,: +5V (PS_ON#,電源工作電壓,),PSON#,在主板上,未開機時,(S5,時,),此信號,PSON#,一直被,pull up,到,+5VSB.,當,User,按下,Power Button,後,一般由,Super I/O,將此信號拉,low,從而通知,Power Supply,送電,.,當實驗時,可以直接把,Power supply,的,PSON#,用導線與,GND,瞬間導通,則此時,Power Supply,開始工作,.,PWROK,PWROK,有的資料也叫,PWRGD,是電源準備,OK,的,信號,.,Power Supply,中會有,PWROK,更多的在主板上,且分很多種,如,CPU_PWRGD, NB_PWRGD,VRMPWRGD, VTT_PWRGD,.,當電源送出的,+3.3V and +5V,達到,Normal,值的,95%,時,由,Power,Supply,送出此信號,.,當,+3.3V or +5V,掉到,Normal,的,95%,以下時,Power Supply,就會把此信號拉,Low.,當主板收到此信號時,表明電源已經準備,ok,可以開始動作,.,但是大部分情況下,我們不會使用此信號來通知主板動作,(,主板上此,PIN,一般空接,),.,而是使用專門的,ASIC,來偵測,+3.3V and +5V,電壓,當電源發出的電壓符合要求時,由,ASIC,發出,PWROK,信號通知主板動作,.,PS.,ASIC,:,Application,Specific Integrated Circuit,是专用集成电路,.,目前,在集成,电路界,ASIC,被认为是一种为专门目的而设计的集成电路,PWROK,The PWRGD_3V is a function of PWRGD_PS, nSLP_S3.,The 1-0 transition of nSLP_S3 will cause an immediate 1-0 transition of PWRGD_3V.,The 0-1 transition of PWRGD_PS will cause a 0-1 transition of PWRGD_3V. The PWRGD_3V is either immediate of after a 100ms to 120ms delay from the 0-1 transition of PWRGD_PS.,+12V,+5V,3.3V,S0 State,PS_ON#,PWRGOOD_PS,400ms,PWRGD_3V,12V,5V,3.3V,PLTRST#,PLTTST,信號是對所有,main Power,信號的,reset,進行時序控制,.,上電原理,Power-up Sequence,G3 State,G3-S5,S5-S0,S3-S0,Power-Down Sequence,S0-S5,S0-G3 (AC Power Loss),上電原理,開機上電過程,ATX,POWER,MOS,ICH,MCH,SIO,CPU,SW_ON#,5VSB,PS_ON#,PWRGD_PS,H_PWRGD,SLP_S3#,32.768KHZ,PWRGD_3V,PWRGD_3V,+/-12V,+/-5V,3.3V,3VSB,上電原理,:,上電過程,上電源由,5VSB,3VSB,按開關後,SW_ON#,對地,short,被拉低,發到,ICH,使,SLP_S3#,拉高,SIO,偵測到此信號後,拉低,PS_ON#,同时把,PS_ON#,送到電源,此時電源發出,+/-12v,+/-5v,+3.3v,電壓,待穩定輸出,90%,後,電源發出,PWRGD_PS,至,SIO,SIO,再發出,PWRGD_3V,至南北橋,南橋偵測到此信號後發出,H_PWRGD,至,CPU.,此時主板開始工作,.,電源時序,1.,PC,電源不僅輸出電壓，還要與主機板有信號聯繫，兩者在時間次序上有一定的關係，這就叫做時序。時序是電源與主機板良好配合的重要條件，也是導致電腦無法正常開關機，以及電源與主機板不相容的最常見原因。,2.,時序中最重要的是電源輸出電壓,(,通常以,+5V,為代表,),與,P.G,信號，以及,PS_ON#,信號之間的關係。,P.G,信號由電源控制，代表電源是否準備好，,PS_ON#,信號則由主機板控制，表示是否要開機。,3.,兩個信號都是通過,2,4,芯的主機板電源線來連接的，電腦開關機的工作過程是這樣的：電源在交流線通電後，輸出一個電壓,+5VSB,到主機板，主機板上的少部分線路開始工作，並等待開機的操作，這叫做待機狀態；,上電原理,4.,當按下主機開關時，主機板就把,PS_ON#,信號變成低電平，電源接到低電平後開始啟動並產生所有的輸出電壓，在所有輸出電壓正常建立後的,0.10.5,秒內，電源將會把,P.G,信號變成高電平傳回給主機板，表示電源已經準備好，然後主機板開始啟動和執行。,5,.,正常關機時，主機板在完成所有關機操作後，把,PS_ON#,信號恢復成高電平，電源關閉所有輸出電壓和,P.G,信號，只保留,+5VSB,輸出，整個主機又恢復到待機狀態。,上電原理,power,的時序,G3 S0,時序,S0 S5 S0,時序,Reset,PWROK,ICH,NB_RST#,CPURST#,MCH,CPU,MB,上外設部件的,RESET#,信號一般是取南橋發出的,一個,RESET#,信號經過驅動,提供給其他部件使用,(LAN,IDE,等,),Reset,主要用來,Question,Please list below signal in sequence when the system power up.,1. (A)3.3V (B)+3.3VSB (C)RSMRST (D)RTCRST# (E)PCIRST,2. (A) VCORE (B)+3.3V (C),Vcc_pwm,(D) CPUPWRGD (E)CPURST#,3. (A) +3.3V (B)+3.3V_DUAL (C)SLP_S3# (D) PSON# (E) PWROK,4. (A) REFCLK (B)+3.3V (C) PERST#,