蒙特卡洛分析

Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,Monte Carlo simulation,for better yield and performance,-A tutorial,start,System requirement,Statistical analysis include process, mismatch effects,Initial design,Design meets the goal ?,end,NO,YES,Monte Carlo simulation,for better yield and performance,Some design may degrade in performance,Overall design yield could be unexpectedly low,If fabrication process parameter and device mismatch effect on same die are not taken in to account then,Hence statistical analysis must find a high place in design cycle,We will perform Monte Carlo analysis on an RF-front end LNA and compare the result if no statistical analysis is done.,We will also see how to analyze yield and scalar data in Monte Carlo with the help of Low pass filter example.,Monte Carlo simulation,Monte Carlo simulation(example),Linearity,Input matching,Bias N/W,Output matching,Cascode arch.to reduce feedback capacitance,RF-front end (LNA,),Knowing System requirement,Initial design based on requirement like noise,gain,narrow or wide band.,Monte Carlo simulation,Cadence simulation setup,(Normal),Choosing affirma analog artist,2.,Choosing,Spectre,simulator,Choosing model file,which contains all MOS,reg.,cap model parameters.,Monte Carlo simulation,1.Choose setup, model libraries,2.Browse and choose model file in the directory,Cadence simulation setup,(Normal),Set up analysis(dc,ac,sp etc.),create netlist and run simulator,Monte Carlo simulation,1.Choose analysis to run,2.Choose output to plot,3.Create netlist and run,Cadence simulation setup,(Normal),Plotting results,Monte Carlo simulation,1.Choose direct plot for analysis,2.Click to view the desired result,3.Analyze waveform,Cadence simulation setup,(Normal),Monte Carlo modeling in Cadence,spectre,simulator,Process Section,-,describes manufacturing parameter,their statistical variation and a model for device that calculates its(width,length,cap,res. Etc.)according to process parameter,.,Design- Specific Section,designer according to his need can specify Monte Carlo analysis.For example in a current mirror circuit,matched transistors are used and designer can give some correlation factor between these matched transistor.,Monte Carlo simulation,Cadence simulation setup,(Monte Carlo),Typical Model File,Process Section,All parameter sets to their nominal value ,no statistical variation defined,Model (,NMOSs,Rg,) is calculated using nominal parameter value,2,1,Monte Carlo simulation,Cadence simulation setup,(Monte Carlo),Defining process,mismatch parameter as statistically assigned value,Assesses the device mismatch on different die, which could have gone through some different process parameters during fabrication.,Assesses the device mismatch on same die,which could have gone through some different process parameter.,Variation defined as a distributed function,Monte Carlo simulation,Process Section,Cadence simulation setup,(Monte Carlo),Design Specific Section,This includes the circuit connectivity(two resistors, and corresponding current sources that feed them),Defining correlation between two devices(R1,R2),Note,:,Alternatively this information can also be inserted through Artist Monte Carlo Tool.,Monte Carlo simulation,Cadence simulation setup,(Monte Carlo),Monte Carlo simulation,Model file used for LNA example,Note,This is not based on foundry data but modeled for illustrative purposes.,Cadence simulation setup,(Monte Carlo),Monte Carlo simulation,After Initial design that meets the system requirement,statistical analysis must have to be carried out.,Make sure the addition of process and mismatch parameter section in model file.,Make certain to include the particular section (for,exa,.Stats in,spectre,) in simulation model library,Go to tool,Monte Carlo in affirma analog artist,Cadence simulation setup,(Monte Carlo),Monte Carlo simulation,Choose no of iteration(default=100),1.Choose which variation to include,Process,device mismatch effect on two diff.die,Mismatchdevice mismatch effect on same die,2.Click if you want to see the family of curve i.e. curve from each iteration,3.Define the expressions / signals on which Monte Carlo analysis will be performed,.,Note,: calculator can also be used to get these expression,Finally run the analysis,Cadence simulation setup,(Monte Carlo),Monte Carlo simulation,(Analyzing waveform),Matching,Normal simulation,(without statistical variation),Monte Carlo Simulation,(with statistical variation),Process parameter and mismatch effect,Input & Output matching N/W,DEGRADES,Overall design performance (noise,gain etc.),DEGRADES,S11,S22,Monte Carlo simulation,(,Analyzing waveform),Matching(VSWR),:,It tells how well input and output N/W are matched.,Monte Carlo simulation,Normal simulation,VSWR1,VSWR2,Variations in VSWR,Monte Carlo simulation,(Analyzing waveform),Matching(forward and reverse transmission gain),It has deteriorated the performance significantly, as a minimum S12 and maximum S21 value is desirable.,Normal simulation,Monte Carlo simulation,S12,S21,Monte Carlo simulation,(Analyzing waveform),Normal simulation,Monte Carlo simulation,Stability,:A,Kf,value 1,is desired for an stable amplifier,Kf,value has become 1,and consequently creating a potential,unstability,hence a large margin is required at initial design phase.,Stability factor,Monte Carlo simulation,(Analyzing waveform),Normal simulation,Monte Carlo simulation,Noise Performance,As visible, design has a robust noise performance at desired band(2.4-2.5 GHz),BUT.,Noise figure,Periodic Output noise,Monte Carlo simulation,(Analyzing waveform),But,LNA as an RF-front end has to provide enough gain with maximum noise suppression to maintain an allowable SNR at demodulators input.,It fails to meet the gain requirement,Gain,Monte Carlo simulation,We will quickly go over another example of low pass filter and see how to analyze scalar data and yield through Monte Carlo simulation,Monte Carlo simulation,Initial Design:,Circuit designing according to system requirement,Low-Pass Filter,Monte Carlo simulation,1.Running normal analysis,2.Specifying statistical variation in model file,3.Running Monte Carlo analysis,1,2,3,Cadence simulation setup,(Monte Carlo),Monte Carlo simulation,Simulation shows,db20,and,phase,values are greatly affected by statistical variations introduced in transistor. Hence the need for,redesigning,the circuit,(Analyzing results),Monte Carlo simulation,(Analyzing Scalar data),1.Choose,results,plot Histogram,2.Choose,parameters to plot,3. Analyze the histogram appeared in waveform window,Monte Carlo simulation,1.Choose,results,specification limits,2.Set,bounds,and,limits,3.Choose Results,yield,simple,in analysis window,4.Set suppression value for yield,5.Analyze yield,Only 64% iterations passes the specified limits for bandwidth and,ymax,(Analyzing Yield),Monte Carlo simulation,(PLL Components),Overview,Reference clock,Detector output,Loop filter response,Oscillator output,Clock divider output, Phase/frequency detector determines the difference between the phase or frequency of two signals, The loop filter removes the high-frequencies from the voltage-controlled oscillator (VCO) controlling voltage, The VCO produces and output frequency controlled by a voltage,Monte Carlo simulation,(PLL Components),Noise Sources,Detector noise,VCO noise,- Quantization noise,In PLL design it is highly desirable to be able to see the impact of all noise sources,which in turn affects the overall PLL performance.,Due to reference jitter,Due to variation in control voltage,Due to uncertainty involved in,discretization,Monte Carlo simulation,(VCO),An oscillator is a circuit capable of maintaining electric oscillations.,Frequency of oscillation =1/(LC),1/2,Controlled by voltage dependent capacitance (varactor),Power efficient since bias current is shared between the two transconductors.,Complimentary Cross-Coupled LC VCO,equivalent,For operation in current -limited regime:,VO,=,(4/,) .,I,bias,.,R,eq,(Ideal switching),VO(,apx,) =,I,bias,.,R,eq,(High frequency),Causes of spectral purity degradation (phase noise):,1.) Random noise in the reference input, the PFD, loop filter and VCO (also dividers if the PLL is a frequency synthesizer),2.) Spurious sidebands high energy sidebands with no harmonic relationship to the generated output signal. It is systematic in origin.,Why is spectral purity important?,Monte Carlo simulation,(VCO Phase Noise),Phase noise produces adjacent,channel interference,Phase noise can degrade the,sensitivity of a receiver due to,reciprocal mixing,Monte Carlo simulation,(VCO Phase Noise),How do the process and mismatch variation affect phase noise?,-,we will perform,monte carlo,analysis to assess this,.,Step1,Varying the process parameter only,Step2,investigating the device mismatch(in diff VCO one side mismatched to the other) in presence of process variation,The statistics block contains the distributions for parameters:,Distributions specified in the process block are sampled once per Monte Carlo run, are applied at global scope, and are used typically to represent batch-to-batch (process) variations.,Distributions specified in the mismatch block are applied on a per-,subcircuit,instance basis, are sampled once per,subcircuit,instance, and are used typically to represent device-to-device (on chip) mismatch for devices on the same chip.,Cadence,Spectre,modeling:,Monte Carlo simulation,(VCO Phase Noise) model file,Define statistical blocks in the model file (ideally it should be provided from the foundry),Process section,Mismatch section,Monte Carlo simulation,(VCO Phase Noise),STEP-1,Running Monte Carlo for process variation only,Normal simulation,Monte Carlo simulation,With applied statistical variation(in model file) an increase in noise can be observed, and at this run resulted noise is worst and unacceptable.,Monte Carlo simulation,(VCO Phase Noise),STEP-2,Running Monte Carlo for mismatch in 2 sides of Diff. VCO,Normal simulation,Monte Carlo simulation,Again similar looking but not the same results appears and noise at this run is unacceptable,.,Note:,When the same parameter is subject to both process and mismatch variations, the sampled process value becomes the mean for the mismatch random number generator for that particular parameter.,Monte Carlo simulation,(VCO Phase Noise)-,more insight,To get more insight we will vary only few parameter and check how values are assigned for different run as well as the simulation result,Defining variation for only two parameters in the model file -,-,Vth,-,tox,Monte Carlo simulation,(VCO Phase Noise)-,more insight,Here both,nmos,(,pmos,) transistors have been assigned same process variation.In each run they take on different parameter according to distribution defined,Process variation only,NM0,NM1,PM1,PM0,Monte Carlo simulation,(VCO Phase Noise)-,more insight,Process and Mismatch both variation together,with correlation of 0.2 between the two,nmos,(,pmos,) transistor,As conspicuous each,nmos,(,pmos,) transistor is getting different parameter value in each run.,Monte Carlo simulation,(VCO Phase Noise)-,more insight,Process variation only,Process & mismatch variation,As visible in the case of process variation with device mismatch noise has been increased.,Monte Carlo simulation,(PLL at a glance),In a PLL all these process variation can degrade its overall performance significantly. To see the impact of process variation we probe the output after the loop filter,.,Monte Carlo simulation,As clear in one case control voltage (i.e. loop filter output) is ramping rapidly compare to other and thus will result in different performance.,Monte Carlo simulation,In our design PLL has a settling time of 65 us.To simply run the analysis(transistor level) for this much period may take 2-3 days on a single machine.,To do,monte carlo,simulation even for 10 run will make the situation worse.,To speed up Monte Carlo analysesto make them run in minutes as opposed to days,-We need to reduce the run time and can utilize Parallel simulation.,-Such as variance reduction technique can be employed.,Monte Carlo simulation,(Seed no & parallel simulation),Note:,(1) Input file should have .,scs,extension (for,exa,.input.,scs,),(2)In,spectre,one can not specify different seed from GUI(by default it always takes seed=1).,If Monte Carlo simulation for different seed is required then.,Step 1,.Create netlist(input file),a)Either from analog artist,or,b)Tools,monte carlo, simulationcreate_input_files,Seed,Monte Carlo simulation,Monte Carlo simulation,(Seed no & parallel simulation),Step 2,.,Edit input.,scs,file manually,edit SEED=,?,line,(number you want),Seed,Monte Carlo simulation,Monte Carlo simulation,(Seed no & parallel simulation),Step 3,.Run,spectre,from command line with option for example.,spectre,-,env,artist4.4.6 +log ./,psf,/,spectre,.out -format,psfbin,-raw ./,psf,input.,scs,Here one should execute,spectre,command(or executable file) from the netlist directory.,For example one wants to simulate “PLL” design from command line,Then go to your simulation directory,cd,/simulation/,pll,/,spectre,/schematic/netlist,and here execute,spectre,command,Seed,Monte Carlo simulation,Monte Carlo simulation,(Seed no & parallel simulation),Step 4,.Results can be plotted with either from calculator or from Monte Carlo tool.,Seed=1,Seed=11,Seed=3,Fig:Plots for different seed value simulation,Seed,Monte Carlo simulation,(Seed no & parallel simulation),Another way of doing similar thing(giving different seed value) from GUI would be to start simulation from different run,or say to skip some initial run as shown,in the fig.,But beware skipping these runs could take much longer time for a complex design,Here it will skip first 10 runs and simulate from 11th to 110th run for 100 iteration,This is quite similar to assigning different seed value.,A way around from GUI,Monte Carlo simulation,(Seed no & parallel simulation),Running multiple analysis from one file,This can be done by defining multiple,monte carlo,analysis statement in the input file as shown below,Note: For each analysis a different name to child analysis(for example ac,dc,tran,) and to output file has to be assigned.,Analysis 1,Analysis 2,Monte Carlo simulation,(Seed no & parallel simulation),Running script for executing multiple files (sequentially),This can be done by making an executable file as shown and running it from command window,NOTE:In all cases,spectre,command(or executable file) must be excited from the netlist directory.,These file can be used to simulate different design as well as same design (with different seed value in it),Parallel Simulation,Monte Carlo simulation,(Seed no & parallel simulation),One can easily set up queues, where a particular queue is set up using the built in CadenceLBS system.,1.Create a configuration file:,queueName,numberOfMachines,machine1,numberOfJobs,machine2,numberOfJobs,queue2,numberOfMachines,.,e.g.,parallelQueue,1,linuxMachine,4,2. Pick a machine as your queue manager, and then run:,cdsqmgr,/path/to/the/queue_,config,3. Before running DFII, do:,setenv,LBS_CLUSTER_MASTER,queueMachineName,where,queueMachineName,was the machine you ran,cdsqmgr,on.,4. Then one can submit Artist jobs as distributed as shown in the .,next slide,Parallel Simulation,Monte Carlo simulation,(Seed no & parallel simulation),Setting for distributive processing,1.from analog artist go to,2.set distributive and assign jobs to all machine,Monte Carlo simulation,(Seed no & parallel simulation),References:,1.Lecture notes of,Michael,Perrott,Massachusetts Institute of Technology.,2.,Lecture notes of,Phillip Allen,Georgia institute of technology.,3. Cadence,Spectre,user guide.,4. Inputs from Andrew Beckett, cadence Inc.,