IBMPCAT硬件架构与动作原理

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,IBM PC/AT 硬體架構與動作原理,(1).PC/AT Original Schematics,1.The Blocks Structure,2.Decoder,3.Data Bus Flow,4.Address Bus Flow,5.Other Signals and ISA,(2).KT9 System( ATI RS200MP+ALI M1535+ ),1.System Block Diagram,2.System Start Steps,3.POST(Power-On Self Test),4.BIOS,(3).Differences (versus CPU/PCI,/ISA),1.Introduction,2.CPU Bus Cycle,3.PCI,(4).Introduction the Compact PCI,by JR Jen 01-12-05,Hom Wo 03-12-29,1,IBM PC/AT 原版電路之功能方塊的內容,1.系統時脈電路,2.DRAM解碼電路,3.RAS&CAS產生電路,4.DRAM偵測電路,5.DRAM定址電路,6.ROM Access電路,7.Decoder,8.等待電路,9.刷新要求電路,10.DMA 控制電路,11.系統中斷電路,12.系統計時/計數器電路,13.鍵盤控制器電路,14.及時時脈電路,15.NMI控制電路,16.Shut-down Logic,2,Figure : Decoder(PC/AT original schematic),HLDA,-DMA1CS,-INTR1CS,-T/C CS,-PPI CS,-PG REG CS,-INTR2 CS,-DMA2 CS,-CS287,00 1FH,203FH,405FH,607FH,809FH,A0BFH,C0DFH,E0FFH,XA5,XA6,XA7,XA9,XA8,-ACK,-ACK,+ACK,-MASTER,Y7,7,Y6,9,Y5,10,Y4,11,Y3,12,Y2,13,Y1,14,Y0,15,G2A,4,G2B,5,G1,6,A,1,B,2,C,3,U123,ALS138,3,4,IBM PC/AT IO Port Addresses,1. Range 00HFFH : System board,2. Range 1003FFH : I/O Channel,3. 00H1FH : DMA Controller 1 Registers,4. 20H3FH : Interrupt Controller 1 Register,5. 40H5FH : Programmable Interrupt Timer,6. 60H64H : keyboard Controller buffer,7. 70H : CMOS RAM address register port,5,8. 71H : CMOS RAM data register Port,9. 80H : Manufacturing Test Port,10. 81H8FH : DMA page table address reg.,11. A0HBFH : Programmable interrupt ctrl 2,12. C0HDFH : DMA Controller 2 Register,13. F0HFFH : Math Coprocessor regs.,14. 170H177H : Fixed disk 1 registers,15. 1F0H1F7H : Fixed disk 0 registers,16. 200H20FH : Game control port,17. 201H : Game Port I/O Data,18. 278H27AH : Parallel Port 3 registers,19.2F8H2FFH : Serial Port 2 registers,6,20. 370H377H : Diskette Controller 1 reg,21. 378H37AH : Parallel Port 2 registers,22. 3BCH3BEH : Parallel Port 1 registers,23. 3F0H3FFH : Diskette Controller 0 reg,24. 3F8H3FFH : Serial Port 1 registers,25. 3C0H3CFH : VGA I/O Port registers,7,8042 Control Register(I,/,O Port Address : 61H),Read/Write status,Bit 7 =1 Parity check,Bit 6 =1 Channel check,Bit 5 =1 Timer 2 output,Bit 4 =1 Toggle with each refresh request,Bit 3 =1 Channel check enabled,Bit 2 =1 Parity check enabled,Bit 1 =1 Speak data enabled,Bit 0 =1 Timer 2 gate to speaker enabled,8,System buffer,36 pin slot,SD8SD15,62 pin slot,SD0SD7,U74,80286,U83,82288,U76,80287,U66,ALS245,U67,LS646,U5,ALS245,U102,ALS245,U11,ALS245,74LS612,MC,146818,8042,8254,8237*2,8259*2,U113,ALS245,RAM,ROM,A,0,A23,D8D15,D0,D7,SD,0,SD7,主機板內DATA Bus的流程,External Buffer,SD8SD15,SD,0,SD7,MD8MD15,MD0MD7,D8D15,D0D7,SD,0,SD7,IVL Byte,Buffer,SD8SD15,XD,0,XD7,Memory,Buffer,SD0SD7,9,DIR,DIR245,G,GATE245,74ALS245,A,B,U113,SD0-SD7,SD8-SD15,ALS04,U97,F10,U97,F10,U97,F10,ALS04,DEN,NPCS#,XBHE#,CNRL OFF#,XA0,DT/R#,LSA0,DT/R#,CKB,SRB,DIR,CKA,SRA,A,B,U67,E,1,2,74LS646,G,DIR,B,DT/R#,74ALS245,U66,A,D8-D15,D0-D7,高/低位元組和系統緩衝器簡圖,10,INTA,XIOR,XIOW,I/O,DIR,功能描述,X,0,1,000,H 0F7H,B A,CPU對主機板I/O埠設備讀取,X,0,1,0,F8H 0FFH,A B,CPU對80287埠設備讀取,X,0,1,100,H 3FFH,A B,CPU對擴充板I/O埠設備讀取,X,1,0,000,H 0F7H,A B,CPU對主機板I/O埠設備寫入,X,1,0,0,F8H 0FFH,A B,CPU對80287埠設備寫入,X,1,0,100,H 3FFH,A B,CPU對擴充板I/O埠設備寫入,X,1,X,X,A B,CPU不在I/O的動作,0,X,X,X,B A,8259 送中斷向量給CPU,外在緩衝器控制線路,外在緩衝器,External Buffer的OIR控制得分析,11,SA0SA19,刷新位址,产生器,74LS590,U72,28 S 42,SA,0,SA,19,62,脚 位 扩 充 值,A0,A1,A19,80286,A20,A23,74,LS612,8237*2,ROM,其它与,XBUS,有关的组件,CONVA0,A0,A17 ALS, 244,A19 U75,74ALS,573*3,U56,U60,U73,G OE,A17A23,A1A19,SA0SA7,SA0,74,ALS245*2U48DIR,U38,SA1,SA16,ALS245,U65,DIR,LA17,LA23,LA17,LA23,36脚 位 扩 充 值,A17,A23,A17A19,XA1,XA16,ALE CPU HLDA,MASTER,74,F158*3,SA0,SA18,RAM,MA0MA9,ADDR SEL,DMAAEN,HOLD,MASTER,位址汇流排方块图,12,HLDA,65,U74,80286,ALE,5,U83,82288,RESET,12,U82,82284,11,12,13,U11,ALS08,4,5,6,U80,ALS32,Y,5,Y,7,Y,3,Y,9,A15,10,A,13,A,17,A,11,G,19,U75,ALS244,CPU HLDA,HLDA,-MASTER,ALE,+ACK,GATE ALE,+RESET,HLDA,AEN,BALE,RESET DRV,AEN, BALE, RESET DRV : AT Slot signals.,AEN, BALE, RESET DRV 信號的流程,From AT slot,HLDA,13,S1,4,S0,5,M/IO,67,U74,80286,S1,3,S0,19,M/IO,18,MRDC,8,MWDC,9,IORC,11,IOWC,13,U83,82288,A1,2,A2,8,A3,4,A4,2,G,1,Y1,18,Y2,12,ALS244,D,3,D,4,D,6,D,8,D,9,D,7,D,5,D,2,G,11,OE,1,Q,12,Q,13,Q,14,Q,15,Q,16,Q,17,Q,18,Q,19,ALS 573,ALS573,-CS ROM,F16,GATE ALE,“LOW”,-MEG CS,-LMEG CS,82S147,A23,A22,A21,A20,A19,A18,A17,+REFRESH,-RAM SEL,S0,S1,M/IO#,-MEMR,-MEMW,-LMEGCS,U49,-MEMR,-MEMW,-SMEMR,-SMEMW,-IOR,-IOW,D0,6,D1,7,D2,8,D3,9,D4,11,D5,12,D6,13,D7,14,A6,17,A7,16,A0,1,A1,2,A2,3,A3,4,A4,5,A5,18,A6,19,G,15,U?,Memory Read/Write 於 IO Read/Write 控制信號在CPU於AT slot之間的流程,-LMEG CS : Dccoder Memory 在1MB以內記憶體空間,14,MRDC#,8,MWTC#,9,IOWC#,11,IORC#,12,U83,82288,B,15,B,16,B,17,B,11,B,12,B,18,A,2,A,4,A,8,A,9,A,3,A,5,DIR,1,G#,U89,LS245,IOW#,1,IOW#,2,MEMW#,3,MEMR#,4,U111,8237 *2,CLR,1,PR,4,D,2,CLK,3,Q,5,U77,F74,1,2,3,U77,LS125,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,U87,PAL16L8,U122,- MEMR,-MEMW,-IOR,-IOW,-IOW,-IOR,-MEMW,- MEMR,AT SLOT,SA0,SBHE,-DMA AEN,LOW,PULL UP,-XMEMR,-DMA MEMR,DMA CLK,-RESET,-XMEMR,-DMA MEMR,-XMEMW,-XIOR,-XIOW,XA0,XBHE,+5,XBHE,XA0,+RAS,-MEMW,-IOR,+AIOW,Q1,-IO CS16,-AEN 1,-AEN 2,Q4,+FSYS16,-RES/OWS,DATA CONV,DIR 245,GATE 245,-DMA AEN,-END CYC,Memory Read/Write 与IO Read/Write 控制信號在82288与8237之 間的流程,15,16,KT9 System Block Diagram,17,NS87570,MS1535+,DC to DC Buck Converter,Logic& Delay circuit,-DNBSWON,-NBSWON,-SUSB,-SUSC,SUSON,MAINON,VRON,HWPG_POWER,NPWROK,NB_PWROK,SB_PWROK,CPU_PWRGD,(1),RVCC,(2),(3),(4),(5),(6),(7),PWR BUTTON,KT9 Power On Block Diagram,18,System Start Steps (1),1. Power ON/OFF Button PC87570(PCU),2. PC87570 M1535+(South Bridge),3. M1535+ PC87570,SUS Power(3VSUS,、5VSUS),4. PC87570 Main Power(3V、5V、2.5V),VHcore,-NBSWON,-SUSB/-SUSC,-DNBSWON,SUSON,MAINON,-VRON,19,1. When we push the Power Button, the signal,-NBSWON,will be generated and send to the PCU(PC87570).,2. As the PCU receives the,-NBSWON, it will send the,-DNBSWON,to the south bridge(M1535+).,3. Then the SB asserts,-SUSB,and,-SUSC,signals to the PCU.,4. The PCU will send the,SUSON, MAINON,and,VRON,for suspend power, main power and VHcore generating.,System Start Steps (1),20,4.1,PC87570,SUSON,SC1470,PQ51/PQ16,PQ3/PQ55,2.5VSUS,12VS,PQ8,PQ40,3VSUS,5VSUS,4.2,PC87570,MAINON,PQ61,PQ44,PQ50/PQ39,LP2996,PQ7/PQ57,3VAGP,2.5V,12V,VTT_DDR,PQ8,PQ40,3V,5V,SUSD,MAIND,4.3,PC87570,-VRON,2.5VSUS,HIP6301,VHcore,21,System Start Steps (2),HWPG,5. MAX1632,HWPG-POWER,PC87570,6. PC87570,NPWROK,NB_PWROK,RS200MP (NB),NB_PWROK,U66,PWROK,7.,SB_PWROK,M1535+,Q58Q59,CPU_PWRGD,PWRGOOD,CPU,22,System Start Steps (3),-SYS_RST,8. M1535+,-PCI_RST,-PCI_RST,9.,-NB_PCIRST,RS200MP,SB_PWROK,-PCIRST,I/O Devices,10. RS200MP,-CPU_RST,CPU,*,CPU and all I/O devices have been reset.,23,System Start Steps (4),11. CPU Memory Code Read North Bridge,- Address (A31# A3#) : FFFF FFF0,12. North Bridge : CPU Command PCI Command,CPU Address PCI Address,13. North Bridge Memory Read South Bridge,- Address ( AD31 AD0) : FFFF FFF0,14. South Bridge : PCI Command ISA Command,PCI Address ISA Address,24,System Start Steps (4),11.,CPU will generate the first command- Memory Code Read to the North Bridge, and the Host address - (A31# A3#) : FFFF FFF0.,12. When the NB receives the CPU command and Host address, It will translate the CPU command to PCI command-(Memory Read), and translate the Host Address to the PCI address-(AD31#AD0#):FFFF FFF0.,13. Then the NB sends the PCI command and PCI address to the South Bridge via the PCI Bus.,14. AS the SB receives the PCI command and PCI address, it will translate the PCI command to the ISA command-(MEMR#) and the PCI address to the ISA address-(A19A0):FFFFF.,25,System Start Steps (5),15. South Bridge MEMR# System ROM,- Address ( SA17 SA0 ): 1FFF0,16. ROM Data ISA Data Bus South Bridge,17. South Bridge PCI Data Bus North Bridge,18. North Bridge Host Data Bus CPU,19. CPU: Decode and Execute,(Go To Step 11 : Decode & Execute),26,System Start Steps (5),15. THE SB will drive the MEMR# command to the System ROM and access the ROM address ( SA17 SA0 ): 1FFF0,16. So the ROM Data will be transferred to South Bridge through the ISA Bus,17. And then through the PCI Bus, the South Bridge will send the PCI date to the North Bridge,18. At the last the North Bridge will send Host data to the CPU through the Host Bus.,19. After the CPU fetch the host data which is transferred from North Bridge, it begins to Decode & Execute(Go To Step 11 : Decode & Execute).,27,The first Execution Instruction in PC AT,CPU Address : A31 A3 = FFFF FFF0,CPU : CS: IP = F000:FFF0 FFFF0,ISA Address : SA17 SA0 = 1FFF0,ISA Data : 1FFF0: EA 5B E0 00 F0 30 37 2F,1FFF8: 31 35 2F 39 39 00 FC 00,5.EA 5B E0 00 F0 = Long Jump F000:E05B,30 37 2F 31 35 2F 39 39 = 07/15/99,28,POST (Power-On Self Test) Process,POST tests and initializes the following :,The central processing unit ( CPU ),The ROM BIOS ( checksum ),The CMOS RAM,The Intel 8237 DMA Controller,The keyboard controller,The base 64K System RAM,The Programmable Interrupt controller,29,8. The Programmable Interrupt Timer,9. The cache controller,10. COMS RAM configuration data,11.The CRT controller,12. RAM memory above 64K,13. The keyboard,14. Diskette drive A availability,15. The serial interface circuitry,16. The diskette controller,17. The fixed disk controller,18. Any additional hardware,30,AWARD BIOS POST Test code listing,POST CODE,Award POST Routine Description,C0,Turn off chipset cache.,01,Test processor flag register.,02,Test all processor registers except SS,SP and BP with pattern FF and 00.,03,Initialize Chips(RTC,8254,8237,8259),Reset math coprocessor,Clear CMOS shutdown byte and page register.,04,Test DRAM refresh,05,Blank video,keyboard controller initialization.,07,Test CMOS interface and battery status.,BE,Initialize chipset with power on BIOS defaults.,C1,Memory-presence test.(OEM Specific-Test to size on-board memory),31,C5,C6,Early Shadow.(OEM Specific-Early Shadow enable for fast boot),Cache presence test. ( External cache size detection),08,Setup low memory(base 64K memory test).,09,Early cache initialization (Cyrix CPU initialization,Cache Initialization.),0A,Setup interrupt vector table.,0B,Test CMOS RAM checksum,load default value if test is bad.,0C,Initialize keyboard(detect keyboard type and set NUM_LOCK status),0D,Initialize and detect video adapter interface.,0E,Test video memory,write sign-on message to screen.Setup shadow RAM-Enable shadow according,to setup.,0F,Test DMA controller 0.,10,Test DMA controller 1.,32,11,Test DMA page registers(74612),14,Test Timer 0 counter 2,15,Test 8259-1 interrupt mask register(port 21H),16,Test 8259-2 interrupt mask register(port A1H),17,Test stuck 8259s interrupt bits,18,Test 8259 interrupt functionality,33,IBM PC/AT System RAM Data Area,(1). Range :,00H to 3FFH,Interrupt Vector Table,Interrupt Vector Stored as,offset/segment format,(2). Range :,400H to 4FFH,BIOS Data Area,Data definitions related to BIOS fixed,disk , diskette , Keyboard , video , ,34,The first two words of expansion ROM area,VGA BIOS (CS:IP = C000:0000),ROM Byte Value,0 55H,1 AAH,2 ROM Length in 512-byte blocks,3 Entry point for ROM initialization,( via FAR CALL ),35,Differences (vs. CPU / PCI /ISA ),CPU PCI ISA,1. Speed 66/100/133 33/66 8 MHz,2. Power Vcore & Vio 3.3V 5V,3. Address Bus 32 / (36) 32/64 24 bit,4. Data Bus 64 32/64 16 bit,5. Address/Data Separate,Shared,Separate,36,6. Control Bus ( Commands / Control signals ),CPU PCI ISA,6.1 Types 8/(32) 16 4,6.2 Start ADS- FRAME- BALE,6.3 End Ready- IRDY-&TRDY- IOCHRDY,7. ID VPID0:3 IDSEL- ( Decoder ),37,38,BUS CYCLE DEFINITION,M/IO# D/C# W/R# Bus Cycle Initiated,0 0 0 Interrupt Acknowledge,0 0 1 Halt/Special Cycle,0 1 0 I/O Read,0 1 1 I/O Write,1 0 0 Code Read,1 0 1 Reserved,1 1 0 Memory Read,1 1 1 Memory Write,39,Transaction,REQ4:0# (First Clock),REQ4:0# (Second Clock),4,3,2,1,0,4,3,2,1,0,Deferred Reply,0,0,0,0,0,Rsvd (ignore),0,0,0,0,1,Interrupt Acknowledge,0,1,0,0,0,DSZ#,0,0,Special Transactions,0,1,0,0,0,DSZ#,0,1,Rsvd (Central agent response),0,1,0,0,1,DSZ#,1,Branch Trace Message,0,1,0,0,1,DSZ#,0,0,Rsvd (Central agent response),0,1,0,0,1,DSZ#,0,1,I/O Read,1,0,0,0,0,DSZ#,LEN#,I/O Write,1,0,0,0,1,DSZ#,LEN#,Rsvd(Ignore),1,1,0,0,DSZ#,Memory Read & Invalidate,ASZ#,0,1,0,DSZ#,LEN#,Rsvd ( Memory Write),ASZ#,0,1,1,DSZ#,LEN#,Memory Code Read,ASZ#,1,D/C#=0,0,DSZ#,LEN#,Memory Data Read,ASZ#,1,D/C#=1,0,DSZ#,LEN#,Memory Write(may not be retried),ASZ#,1,W/WB#=0,1,DSZ#,LEN#,Memory Write(may be retried),ASZ#,1,W/WB#=0,1,DSZ#,LEN#,Transaction Type Defined by REQ# Signals,40,Table LEN1:0# Signal Data Transfer Lengths,LEN1:0#,Request Initiators Data Transfer Length,00,0-8 Bytes,01,16 Bytes,10,32 Bytes,11,Reserved,ASZ1:0#,Description,0 0,0= A35:3# 4GB,0 1,4GB=A35:3#64GB,1 x,Reserved,Table ASZ1:0# Signal Decode,41,POWERGOOD Relationship at Power-On,VCCcore,VCC,L2,PWRGOOD,RESET#,Clock,1 ms,Ratio,BCLK,42,Ratio of processor Core Frequency,to,System Bus Frequency,LINT1,LINT0,IGNNE#,A20M#,Reserved,H,L,H,H,3/2,H,H,L,H,2,H,H,H,H,5/2,L,H,L,L,3,L,L,H,L,7/2,L,H,H,L,4,L,L,L,H,9/2,L,H,L,H,5,L,L,H,H,11/2,L,H,H,H,6,H,L,L,L,13/2,H,H,L,L,7,H,L,H,L,15/2,H,H,H,L,8,H,L,L,H,System Bus To Core Frequency Multiplier Configuration,43,Processor,PCI Local Bus,Bridge/,Memory,Controller,Cache,DRAM,LAN,SCSI,Exp Bus,Xface,Base I/Os,ISA/EISA Micro Channel,Audio,Motion video,Graphics,44,ADDRESS PHASE,DATA PHASE,DATA PHASE,DATA PHASE,BUS TRANSACTION,Figure : Basic Read Operation,1,2,3,4,5,6,7,8,9,CLK,FRAME#,AD,ADDRESS,DATA-1,DATA-2,DATA-3,C/BE#,BUS CMD,BE#S,IRDY#,WAIT,DATA TRANSFER,WAIT,DATA TRANSFER,WAIT,DATA TRANSFER,TRDY#,DEVSEL#,45,Command Definition,C/BE3:0# Command Type,0000 Interrupt Acknowledge,0001 Special Cycle,0010 I/O Read,0011 I/O Write,0100 Reserved,0101 Reserved,0110 Memory Read,0111 Memory Write,1000 Reserved,1001 Reserved,1010 Configuration Read,1011 Configuration Write,1100 Memory Read Multiple,1101 Dual Address Cycle,1110 Memory Read Line,1111 Memory Write and Invalidate,46,DATA PHASE,DATA PHASE,DATA PHASE,BUS TRANSACTION,1,2,3,4,5,6,7,8,9,CLK,FRAME#,AD,ADDRESS,DATA-1,DATA-3,C/BE#,BUS CMD,BE#S-3,IRDY#,WAIT,DATA TRANSFER,WAIT,DATA TRANSFER,WAIT,DATA TRANSFER,TRDY#,DEVSEL#,DATA-2,BE#S-1,BE#S-2,ADDRESS PHASE,Figure : Basic Write Operation,47,PCI,COMPLIANT,DEVICE,AD63:32,C/BE7:4#,AD31:00,C/BE3:0#,PAR,Address & Data,Interface Control,FRAME#,IRDY#,TRDY#,STOP#,CLK,SERR#,IDSEL,PERP#,GNT#,REQ#,STOP#,RST#,Arbtration (masters only),Error Reporting,System,TDI,TDO,TCK,TMS,TRST#,64-Bit,Extension,Interface Control,Interrupts,JTAG,(IEEE 1149.1),INTA#,INTB#,INTC#,INTD#,PAR64,REQ64#,LOCK#,ACK64#,Figure : PCI Pin List,Required Pins,Optional Pins,48,Compact PCI feature(part 1),1. 33 and 66 MHz PCI performance,2. 32-and 64-bit data transfers,3. 8 CompactPCI slots per bus segment at 33 MHz,4. 5 CompactPCI slots per bus segment at 66 MHz,5. Industry standard software support,6. 3U small form factor(100 mm by 160 mm),7. 6U form factor(233.35 mm by 160 mm),49,Compact PCI Features(part 2),8. IEEE(1101.1 , 1101.10 and 1101.11 ),Eurocard packaging,9. Wide variety of available I/O,10. System Management Bus,(CompactPCI Specification PICMG 2.0 D3.0,September 24,1999),50,2,3,4,5,6,7,8,1,=,SYSTEM SLOT,=,PERIPHERAL SLOT,+ + + + +,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,+ + + + +,+ + + + +,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,+ + + + +,+ + + + +,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,+ + + + +,+ + + + +,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,+ + + + +,+ + + + +,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,+ + + + +,+ + + + +,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,+ + + + +,+ + + + +,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,+ + + + +,+ + + + +,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,+ + + + +,Figure : 3U CompactPCI Backplane Example,7-p2,2-P2,22,1,25,22,1,25,z a b c d e f,2-P1,51,