逻辑设计基础课件

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,逻辑设计基础,*,第12章 寄存器和计数器,8/14/2024,1,逻辑设计基础,第12章 寄存器和计数器8/25/20231逻辑设计基础,Registers and Register Transfers,Shift Registers,Design of Binary Counters,Counters for Other Sequences,Counter Design Using S-R and J-K,Summary,Outline:,8/14/2024,2,逻辑设计基础,Registers and Register Transfe,12.1Registers and Register Transfers,图12-1: 由D型触发器构成的带置数端的4位寄存器,8/14/2024,3,逻辑设计基础,12.1Registers and Register Tra,8/14/2024,4,逻辑设计基础,8/25/20234逻辑设计基础,Figure 12-2: Data Transfer Between Registers,8/14/2024,5,逻辑设计基础,Figure 12-2: Data Transfer Be,Figure 12-3: Logic Diagram for 8-Bit Register with Tri-State Output,8/14/2024,6,逻辑设计基础,Figure 12-3: Logic Diagram fo,Fig 12-4: Data Transfer Using a Tri-State Bus,8/14/2024,7,逻辑设计基础,Fig 12-4: Data Transfer Using,Fig12-5: N-Bit Parallel Adder with Accumulator,8/14/2024,8,逻辑设计基础,Fig12-5: N-Bit Parallel Adder,Figure 12-6: Adder Cell with Multiplexer,8/14/2024,9,逻辑设计基础,Figure 12-6: Adder Cell with,12.2 Shift Registers,Figure 12-7,8/14/2024,10,逻辑设计基础,12.2 Shift RegistersFigure 12-,Fig 12-8: 8-Bit Serial-In, Serial-Out Shift Register,8/14/2024,11,逻辑设计基础,Fig 12-8: 8-Bit Serial-In, Se,Fig 12-9 图12-8中移位寄存器的典型时序图,8/14/2024,12,逻辑设计基础,Fig 12-9 图12-8中移位寄存器的典型时序图8/2,Figure 12-10: 并行输入输出的右移寄存器,8/14/2024,13,逻辑设计基础,Figure 12-10: 并行输入输出的右移寄存器8/25,8/14/2024,14,逻辑设计基础,8/25/202314逻辑设计基础,Table 12-1: Shift Register Operation,8/14/2024,15,逻辑设计基础,Table 12-1: Shift Register Ope,串行输入一直为SI=0，t,0,时刻D,3,D,2,D,1,D,0,为1011,8/14/2024,16,逻辑设计基础,串行输入一直为SI=0，t0时刻D3D2D1D0为10118,Figure 12-12: Shift Register withInverted Feedback,8/14/2024,17,逻辑设计基础,Figure 12-12: Shift Register,12.3 二进制计数器的设计,计数器的设计过程,画出计数器的状态转换图,得到状态转换表,求出控制函数、输出函数。,画图,检查有无挂起,8/14/2024,18,逻辑设计基础,12.3 二进制计数器的设计 计数器的设计过程画出计数器的状,例题1：,T触发器，计数值为8 (P264),8/14/2024,19,逻辑设计基础,例题1：T触发器，计数值为8 (P264)8/25/2023,现态,C B A,次态,C,+,B,+,A,+,触发器输入,T,C,T,B,T,A,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 0,0 0 1,0 1 1,0 0 1,1 1 1,0 0 1,0 1 1,0 0 1,1 1 1,Table 12-2 State Table for Binary Counter,8/14/2024,20,逻辑设计基础,现态次态触发器输入0 0 00 0 10 0 1,Figure 12-14: Karnaugh Maps for Binary Counter,8/14/2024,21,逻辑设计基础,Figure 12-14: Karnaugh Maps f,Figure 12-13: Synchronous Binary Counter,8/14/2024,22,逻辑设计基础,Figure 12-13: Synchronous Bin,Figure 12-17: 可逆计数器,例题2：,D触发器，计数值为8, 可逆,8/14/2024,23,逻辑设计基础,Figure 12-17: 可逆计数器例题2：D触发器，计,现态,C B A,次态C,+,B,+,A,+,UD,00,10,01,11,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 0,1 1 1,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,x x x,x x x,x x x,x x x,x x x,x x x,x x x,x x x,8/14/2024,24,逻辑设计基础,现态次态C+ B+ A+UD001001110 0 00,得到表达式：,D,A,= A,+,=A (U+D),D,B,= B,+,=B (UA+DA),D,C,= C,+,=C (UBA+DBA),8/14/2024,25,逻辑设计基础,得到表达式：8/25/202325逻辑设计基础,Figure 12-18: Binary Up-Down Counter,8/14/2024,26,逻辑设计基础,Figure 12-18: Binary Up-Down,Fig 12-19ab: Loadable Counter with Count Enable,(a),例题3：,D触发器组成3位计数器, 有Ld(置数)和Ct(计数),(b),8/14/2024,27,逻辑设计基础,Fig 12-19ab: Loadable Counter,Figure 12-20: Circuit for Figure 12-19,8/14/2024,28,逻辑设计基础,Figure 12-20: Circuit for Fig,Figure 12-21: State Graph for Counter,Table 12-3: State Table for Figure 12-21,12.4 其它顺序的计数器,8/14/2024,29,逻辑设计基础,Figure 12-21: State Graph for,现态,C B A,次态,C,+,B,+,A,+,触发器输入,T,C,T,B,T,A,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,1 0 0,- - -,0 1 1,0 0 0,1 1 1,- - -,- - -,0 1 0,1 0 0,x x x,0 0 1,0 1 1,0 1 1,x x x,x x x,1 0 1,8/14/2024,30,逻辑设计基础,现态次态触发器输入0 0 01 0 01 0 0,Figure 12-22,8/14/2024,31,逻辑设计基础,Figure 12-228/25/202331逻辑设计基础,Figure 12-23: Counter Using T Flip-Flops,8/14/2024,32,逻辑设计基础,Figure 12-23: Counter Using T,Figure 12-24: Timing Diagram for Figure 12-23,8/14/2024,33,逻辑设计基础,Figure 12-24: Timing Diagram,Figure 12-25:,State Graph for Counter,8/14/2024,34,逻辑设计基础,Figure 12-25: State Graph for,Table 12-5 S-R Flip-Flop Inputs,12.5 用SR和JK型设计Counter,8/14/2024,35,逻辑设计基础,Table 12-5 S-R Flip-Flop Inpu,例题1：,用SR型实现图12-21的计数器,(P269),8/14/2024,36,逻辑设计基础,例题1：用SR型实现图12-21的计数器 (P269)8/2,Fig12-27: Counter of Figure 12-21 Using S-R Flip-Flops,8/14/2024,37,逻辑设计基础,Fig12-27: Counter of Figure 12,(c) Logic circuit,8/14/2024,38,逻辑设计基础,(c) Logic circuit8/25/202338逻辑,Table 12-7 J-K Flip-Flop Inputs,8/14/2024,39,逻辑设计基础,Table 12-7 J-K Flip-Flop Inp,例题2：,用JK型实现图12-21的计数器,(P275),8/14/2024,40,逻辑设计基础,例题2：用JK型实现图12-21的计数器 (P275)8/2,Figure 12-28: Counter of Figure 12-21 Using J-K Flip-Flops,8/14/2024,41,逻辑设计基础,Figure 12-28: Counter of Figur,Figure 12-28: Counter of Figure 12-21 Using J-K Flip-Flops,8/14/2024,42,逻辑设计基础,Figure 12-28: Counter of Figur,触发器类型,输入端,Q=0,Q=1,Q,+,=0,Q,+,=1,Q,+,=0,Q,+,=1,D型,D,0,1,0,1,T型,T,0,1,1,0,SR型,S R,0 X,1 0,0 1,X 0,JK型,J K,0 X,1 X,X 1,X 0,Table 12-9,12.6 总结,8/14/2024,43,逻辑设计基础,触发器类型输入端Q=0Q=1Q+=0Q+=1Q+=0Q+=1,