(内存基本知识)DRAM工作原理课件

DRAM工作原理DRAM工作原理DRAM工作原理工作原理 DRAM工作原理工作原理Dynamic Random Access MemoryEach cell is a capacitor+a transistorVery small sizeSRAM uses six transistors per cellDivided into banks,rows&columnsEach bank can be independently controlledDRAMDynamic Random Access MemoryDRMain MemoryEverything that happens in the computer is resident in main memoryCapacity:around 100 Mbyte to 100 Gbyte Random access Typical access time is 10-100 nanosecondsWhy DRAM for Main Memory?Cost effective(small chip area than SRAM)High Speed(than HDD,flash)High Density(Gbyte)Mass Production Main memoryMain MemoryMain memoryNotation:K,M,G In standard scientific nomenclature,the metricmodifiers K,M,and G to refer to factors of 1,000,1,000,000 and 1,000,000,000 respectively.Computer engineers have adopted K as thesymbol for a factor of 1,024(210)K:1,024(210)M:1,048,576(220)G:1,073,741,824(230)DRAM density 256M-bit 512M-bitNotation:K,M,GDRAM DensityDRAM DensityWhat is a DRAM?DRAM stands for Dynamic Random Access Memory.Random access refers to the ability to access any of the information within the DRAM in random order.Dynamic refers to temporary or transient data storage.Data stored in dynamic memories naturally decays over time.Therefore,DRAM need periodic refresh operation to prevent data loss.What is a DRAM?Memory:DRAM position Semiconductor memory device ROM:Non volatile Mask ROM EPROM EEPROM Flash NAND:low speed,high density NOR:high speed,low density RAM:Volatile DRAM:Dynamic Random Access Memory SRAM:Static Random Access Memory Pseudo SRAMMemory:DRAM positionDRAM Trend:Future High Speed-DDR(333MHz500MHz),DDR2(533800Mbps),DDR3(8001600Mbps)-Skew-delay minimized circuit/logic:post-charge logic,wave-pipelining-New Architecture:multi-bank structure,high speed Interface Low Power-5.5V=3.3V(sdr)=2.5V(ddr)=1.8V(ddr2)=1.5v(ddr3)=1.2v?-Small voltage swing I/O interface:LVTTL to SSTL,open drain-Low Power DRAM(PASR,TCSR,DPD)High Density-Memory density:32MB=64MB=.1GB=2GB=4GB-application expansion:mobile,memory DB for shock(than HDD)-Process shrink:145nm(03)=120nm(04)=100nm=90nm=80nm Other Trends-Cost Effectiveness,Technical Compatibility,Stability,Environment.ReliabilityDRAM Trend:FutureStatic RAMSRAMBasic storage element is a 4 or 6 transistor circuit which will hold a 1 or 0 as long as the system continues to receive powerNo need for a periodic refreshing signal or a clockUsed in system cacheFastest memory,but expensiveSRAM ElementEnable Line/Bit LineBit LineStatic RAMSRAMSRAM ElementEnabDynamic RAMDRAMDenser type of memoryMade up of one-transistor(1-T)memory cell which consists of a single access transistor and a capacitorCheaper than SRAMUsed in main memoryMore complicated addressing schemeDRAM CellWord LineBit LineDynamic RAMDRAMDRAM CellWord LRefresh in DRAMsCapacitor leaks over time,the DRAM must be“REFRESHED”.DRAM CellWord LineBit LineCapacitance LeakageRefresh in DRAMsCapacitor leakSRAM vs.DRAMSRAM vs.DRAM(内存基本知识内存基本知识)DRAM工作原理课件工作原理课件DRAMLeadFrameandWirebondingDRAM Lead Frame and Wire bondiDRAMArchitectureDRAM ArchitectureSDRAM has the multi bank architecture.Conventional DRAM was product that have single bank architecture.The bank is independent active.memory array have independent internal data bus that have same width as external data bus.Every bank can be activating with interleaving manner.Another bank can be activated while 1st bank being accessed.(Burst read or write)MultiBankArchitectureSDRAM has the multi bank archiDRAMMultiBankArchitectureDRAM Multi Bank ArchitectureDRAMSingleBankArchitectureDRAM Single Bank Architecture(内存基本知识内存基本知识)DRAM工作原理课件工作原理课件DRAMBlockDiagram(1)DRAM Block Diagram(1)DRAMBlockDiagram(2)DRAM Block Diagram(2)DRAMCoreArchitectureDRAM Core ArchitectureDRAMAddressDRAM AddressDRAMCoreArchitectureDRAM Core Architecture16bitDRAMCore16bit DRAM CoreDRAMDataPathDRAM Data PathDRAM1T-1CstructureDRAM 1T-1C structureuRAS:row address strobeuCAS:column address strobeuWE:write enableuAddress:code to select memory cell locationuDQ(I/O):bidirectional channel to transfer and receive datauDRAM cell:storage element to store binary data bituRefresh:the action to keep data from leakageuActive:sense data from DRAM celluPre charge:standby stateDRAMKeywordRAS:row address strobeDRAM KeDRAM cell array consist of so many cells.One transistor&One capacitorSmall sense amplifierLow input gain from charge sharingCS:Small storage capacitor:25fFCBL:Large parasitic capacitor:over 100fFVc:Storage voltageVCP:half Vc for plate biasVBLP:half Vc for BL pre charge bias(initial bias)DRAMCellDRAM cell array consist of so DRAM Array OverviewSimplified ExampleDRAM Array OverviewSimplified Activating a RowActivating a RowMust be done before a read or writeJust latch the row address and turn on a single wordlineActivating a RowActivating a RWritingWritingA row must be activeSelect the column addressDrive the data through the column muxStores the charge on a single capacitorWritingWritingReadingReadingA row must be activeSelect the column addressThe value in the sense-amplifier is driven back outReadingReadingThe Sense-AmplifierSense-AmplifierA pair of cross-coupled invertersBasically an SRAM elementWeaker than the column muxWrite data will“outmuscle”the sense-amplifierKeeps the data at full levelThe Sense-AmplifierSense-AmpliPrechargePrechargeInactive state(no wordlines active)Precharge control line highTies the two sides of the sense-amp togetherThis makes the bitlines stay at VDD/2Only stable as long as the precharge control line is highotherwise this is unstable!No capacitors connectedPrechargePrechargeActivation RevisitedActivationTurn off the precharge control lineMakes the sense-amp unstableit wants to go to either 0 or 1 instead of staying at VDD/2A very very very short time later,turn on the wordline of the row to be activated.Couples the capacitor onto the bitlinesThis“tips”the bitlines to hold the stored value.The sense-amp amplifies the capacitor back to full value.(hence the name!)Activation RevisitedActivationDRAM RefreshBecause the stored memory value is stored on a capacitor(that has resistive leakage),the memory is constantly“forgetting”its contents.Eventually,the charge on the capacitor wont be enough to tip the sense-amp in the right direction.But,activating a row restores the cells on that row to their full value.There is an explicit refresh command that just activates and immediately deactivates a row.The DRAM has an internal counter that contains the next row to be refreshed and increments every time a refresh command is issued.DRAM RefreshBecause the storedDRAM RefreshData Retention Time DRAM Cell consists of capacitance which has leakage as time Retention time is period for maintaining its data especially 1 data Usually,DRAM Cell refresh period is 64msRefresh Timing tREF:Real cell retention time(Device characteristic),ex)90ms(Hot)tRFC:Refresh command operating time,ex)75nsRefresh Spec.Burst Refresh:64ms Distribute refresh-128Mb device(12 Row address):64ms/4K=15.6us-256Mb device(13 Row address):64ms/8K=7.8usDRAM RefreshData Retention TimAUTO Refresh When this command is input from the IDLE state,the synchronous DRAM starts autorefresh operation.During the auto-refresh operation,refresh address and bank select address are generated inside the Synchronous DRAM.For every auto-refresh cycle,the internal address counter is updated.Accordingly,8192times are required to refresh the entire memory.Before executing the auto-refresh command,all the bank must be IDLE state.In addition,since the Precharge for all bank is automatically performed after auto-refresh,no Precharge command is required after auto-refresh.AUTO Refresh When this coSelf Refresh Self-Refresh EntrySELF:When this command is input during the IDLE state,the Synchronous DRAM starts self-refresh operation.After the execution of this command,selfrefresh continues while CKE is Low.Since self-refresh is performed internally and automatically,external refresh operations are unnecessary.Self-Refresh ExitSELFX:When this command is executed during self-refresh mode,the Sync DRAM can exit from self-refresh mode.After exiting from self-refresh mode,the Sync DRAM enters the IDLE state.,no Precharge command is required after auto-refresh.Self Refresh Self-Refresh Mode RegisterSpecial command to initialize the DRAMBurst lengthInterleavingCAS Latency(read command to read data in clocks)For DDR,DLL reset is also hereMode RegisterSpecial command tMRS Block DiagramMRS Block DiagramMode RegisterBecause the stored memory value is stored on aMode RegisterBecause the storeExtended Mode RegisterSpecial command to initialize DDR DRAMDDR onlydont use for SDRDLL EnableDrive StrengthExtended Mode RegisterSpecial DRAM InterfaceCommand SignalsCAS#,RAS#,WE#,CS#CS#+CAS#=ReadCS#+WE#+CAS#=WriteCS#+RAS#+CAS#=RefreshCS#+RAS#=ActivateCS#+WE#=Burst StopCS#+WE#+RAS#=PrechargeCS#+WE#+CAS#+RAS#=MRS or EMRSAll others:NOPOther signals:CLK,DATA,DQSDRAM InterfaceCommand SignalsDRAM InterfaceAll signals go from the host to the memory except DQS and data which are bi-directional.DRAM InterfaceAll signals go fRead CycleTypical Read CycleBurst Length 4CAS Latency=3Read CycleTypical Read CycleWrite CycleTypical Write CycleBurst Length 4Write latency is always zeroWrite CycleTypical Write CycleData ClockingCLK is always driven by the hostDQS is driven by whoever is driving the dataNV chip drives on write cyclesMemory chip drives on read cyclesThis scheme is called“source-synchronous clocking”Eliminates a lot of the timing headaches from SDRAdds marginData ClockingCLK is always driLatenciesAll kindsActivate to PrechargeLast write data to prechargeActivate to ReadActivate to WriteRefresh cycle timeRefresh intervalMinimum row active timeYadda yadda yaddaControlled by PFB_TIMING0,PFB_TIMING1,PFB_TIMING2LatenciesAll kindsWrite CycleWrite CycleDLLsA DLL is a Delay-Locked LoopNo transistor can switch in zero time,so there will be a delay between clock and DQS on readsBut,it would make it easier if DQS was always in phase with clock.DLL-off clock-DQS delay not in the specVaries between memory vendorsRe-creates a delayed version of its input clockKeeps DQS on reads aligned with clocksIts an analog circuit and is sensitive to noiseCan lose lock on the input clock if the signal is not clean or the DLL power supply is noisy.DLLsA DLL is a Delay-Locked LoDLLsDLL onDLL offDLLsDLL on tAA,tAC,tOH tRCD,tRP Set-up/Hold time Vih,Vil Voh,Vol Ioh,IolTimingParameters tAA,tAC,tOHTiming ParametSDRAMTimingDiagramSDRAM Timing DiagramtAA,tAC,tOH(SDRAM)tAA,tAC,tOH(SDRAM)Setup/holdtime Timing for latching data in Input buffer CLK rising edge is strobe for data(SDRAM)DQS rising&falling edge is strobe for data(DDR SDRAM)During Setup&time,there is no abnormal signal allowedSetup/hold time Timing VIH/VILVIH/VILVOH/VOLVOH/VOLIOH/IOLIOH/IOLDCSpecDC SpecThanks!Thanks!