第1章-集成电路设计概述课件

第1章-集成电路设计概述*4 4认识晶圆和集成电路*5 5裸片*6 6键合(连接到封装的引脚)*7 7封装，成品*8 8应 用*9 91.1 集成电路的发展集成电路的发展1.2 集成电路设计流程及设计环境 1.3 集成电路制造途径1.4 集成电路设计知识范围*101019471947年年1212月月1616日日,美国贝尔实美国贝尔实验室验室(Bell-Lab),William Bell-Lab),William ShockleyShockley领导的研究小组发现领导的研究小组发现了晶体管效应。了晶体管效应。19481948年年6 6月向全世界公布。月向全世界公布。19561956年年，W.W.Shockley,Shockley,John John Bardeen,Bardeen,Walter Walter Brattain Brattain 获获诺诺贝贝 尔尔 物物 理理 奖奖,for for their their researches researches on on semiconductors semiconductors and and their their discovery discovery of of the the transistor effecttransistor effect 图1.1 最原始的点接触式晶体管1.1 集成电路的发展*1111硅时代的飞跃集成电路的诞生Fig1.2 Jack Kilbys first Integrated Circuits(IC)of the world*1212表表1.1 1.1 集成电路工艺、电路规模和产品的发展概集成电路工艺、电路规模和产品的发展概况况P-IV,手机芯片等P-III专用处理器,虚拟现实机,灵巧传感器16位32位微处理器,复杂外围电路 8位微处理器,ROM RAM计数器复接器加法器平面器件:逻辑门触发器结型晶体管和二极管结型晶体管典型产品50M10M1M-10M20K-1M1K-20K100-1K1011产品芯片上大约晶体管数目SOCGSIULSIVLSILSIMSISSI分立元件晶体管工艺200320001990198019711966196119501947年份*1313摩尔定律(Moores Law)Moores law:the number of components per IC doubles every 18 months.Moores law hold to this day.*1414Intel的CPU验证摩尔定律*1515Fig1.4 Intel 4004 Micro-Processor by by 1971 1971 the the 4004 4004 the the first first 4-bit 4-bit microprocessor microprocessor was was in in production.production.The The 4004 4004 was was a a 3 3 chip chip set set with with a a 2kbit 2kbit ROM ROM chip,chip,a a 320bit 320bit RAM RAM chip chip and and the the 4bit 4bit processor processor each each housed housed in in a a 16 16 pin pin DIP DIP package.package.The The 4004 4004 processor processor required required roughly roughly 2,3002,300 transistors transistors to to implement,implement,used used a a silicon silicon gate gate PMOSPMOS process process with with 1010 mm line line widths,widths,had had a a 108kHz 108kHz clock clock speed speed and a die size of 13.5mmand a die size of 13.5mm2 2.*1616Intel Pentium(II)-1997Fig1.50.35m CMOSdie size:209 mm2*171780年代以后DRAM的发展表 1.2*181812英寸(300mm)0.09微米是目前量产最先进的CMOS工艺线关心工艺线关心工艺线*1919集成电路技术发展趋势1)1)特特征征尺尺寸寸：微微米米亚亚微微米米深深亚亚微微米米，目目前前的的主主流流工工艺艺是是0.350.35、0.250.25和和0.18 0.18 mm，0.150.15和和 0.130.13 m,m,90nm,65nm,45nm90nm,65nm,45nm已已开开始始走走向向规规模模化化生产；生产；2)2)电路规模：电路规模：SSISSISOCSOC；3 3）晶圆的尺寸增加）晶圆的尺寸增加,当前的主流晶圆的尺寸为当前的主流晶圆的尺寸为8 8英寸英寸,正在向正在向1212英寸晶圆迈进；英寸晶圆迈进；4 4）集成电路的规模不断提高）集成电路的规模不断提高,先进的先进的CPU(P-IV)CPU(P-IV)已超过已超过40004000万晶体管万晶体管,DRAMDRAM已达已达GbGb规模；规模；*20205 5）集成电路的速度不断提高集成电路的速度不断提高,人们已经用人们已经用0.10.13 3 mm CMOSCMOS工艺做出了主时钟达工艺做出了主时钟达 2GHz2GHz的的CPU CPU；10Gbit/s 10Gbit/s的高速电路和的高速电路和 6GHz6GHz的射频电路；的射频电路；6 6）集成电路复杂度不断增加，系统芯片或称芯片系统）集成电路复杂度不断增加，系统芯片或称芯片系统SoC(System-on-Chip)SoC(System-on-Chip)成为开发目标；成为开发目标；7 7）设计能力落后于工艺制造能力；）设计能力落后于工艺制造能力；8 8）电路设计、工艺制造、封装的分立运行为发展无生产）电路设计、工艺制造、封装的分立运行为发展无生产线（线（FablessFabless）和无芯片（和无芯片（ChiplessChipless）集成电路设计提集成电路设计提供了条件，为微电子领域发展知识经济提供了条件。供了条件，为微电子领域发展知识经济提供了条件。集成电路技术发展趋势集成电路技术发展趋势*21211.1 集成电路的发展1.2 集成电路设计流程及设计环境集成电路设计流程及设计环境 1.3 集成电路制造途径1.4 集成电路设计知识范围*2222集成电路发展的前三十年中，设计、制造和封装都是集中在半导体生产厂家内进行的，称之为一体化制造(IDMIDM，Integrated Device ManufactureIntegrated Device Manufacture)的集成电路实现模式。近十年以来，电路设计、工艺制造和封装开始分立运行，这为发展无生产线（Fabless）集成电路设计提供了条件，为微电子领域发展知识经济提供了条件。IDM与Fabless集成电路实现*2323Fabless and Foundry DefinitionWhat is What is FablessFabless?IC Design based on foundries,i.e.IC Design based on foundries,i.e.IC Design unit without any process owned by IC Design unit without any process owned by itself.itself.What is What is FoundryFoundry?IC manufactory purely supporting fabless IC IC manufactory purely supporting fabless IC designers,i.e.designers,i.e.IC manufactory without any IC design entity of IC manufactory without any IC design entity of itself.itself.*2424Relation of F&F(无生产线与代工的关系)LayoutChipDesignkitsInternetFoundryFabless设计单位代工单位*2525Relation of FICD&VICM&Foundry无生产线IC设计-虚拟制造-代工制造Foundry IFoundry IIFICD:Fabless IC DesignerVICM:Virtual IC Manufacture(虚拟制造)(MOSIS,CMP,VDEC,CIC,ICC)FICD 1FICD 2FICD 3FICD 4FICD nVICMVICM*2626Fabless IC Design+Foundry IC ManufactureFabless FoundryDesignkits*2727Process Design KitsPDKPDK stands stands for for Process Process Design Design Kits.Kits.It It s s abstract abstract definition definition is is everything everything a a Circuit Circuit Design Design development development team team needs needs to to know know about about a a process process technologytechnology to to do do device-level device-level design design as as viewed viewed through through the the Cadence electronic design environmentCadence electronic design environment.A A design design environment environment that that includes includes schematic schematic symbols,simulation models,and layout generationsymbols,simulation models,and layout generation.LayoutLayoutSchematicSchematic L=2W=10Model:2.5V NPNSimulationSimulation*28281.1 集成电路的发展1.2 集成电路设计流程及设计环境 1.3 集成电路制造途径集成电路制造途径1.4 集成电路设计知识范围*2929国内可用Foundry(代客户加工代客户加工)厂家*3030国内在建、筹建Foundry(代客户加工代客户加工)厂家上海:“中芯”，8”,0.25m,2001.10 “宏力”，8”,0.25m,2002.10 “华虹-II”，8”,0.25m,筹建 台积电(TSMC),已宣布在松江建厂北京:首钢NEC,8”,0.25m,筹建天津:Motolora,8”,0.25m,动工苏州:联华(UMC),已宣布在苏州建厂*3131表1.4 境外可用Foundry工艺厂家PeregrinePeregrine(SOI/SOS)(SOI/SOS)VitesseVitesse(GaAs/InP)(GaAs/InP)IBM/JazzIBM/Jazz(SiGe)(SiGe)OMMIC(GaAs)OMMIC(GaAs)Win(Win(稳懋稳懋)(GaAs)(GaAs)AgilentAgilent(CMOS)(CMOS)AMSAMS(CMOS/BiCMOS)(CMOS/BiCMOS)UMC(UMC(联华联华)(CMOS/BiCMOS)(CMOS/BiCMOS)OrbitOrbitSTMSTM(CMOS/BiCMOS)(CMOS/BiCMOS)DongbuDongbu(东部东部)Chartered(Chartered(特许特许)(CMOS/BiCMOS)(CMOS/BiCMOS)TSMC(TSMC(台积电台积电)(CMOS/BiCMOS)(CMOS/BiCMOS)美国美国欧洲欧洲韩国韩国新加坡新加坡台湾台湾*3232芯片工程与多项目晶圆计划Many ICs for different projects are laid on one Many ICs for different projects are laid on one macro-IC and fabricated on wafersmacro-IC and fabricated on wafersThe costs of masks and fabrication is divided by all The costs of masks and fabrication is divided by all users.Thus,the cost paid by a single project is low users.Thus,the cost paid by a single project is low enough especially for R&Denough especially for R&DThe risk of the ICThe risk of the IC s R&D becomes low s R&D becomes low Single ICMacro-IC MPW(layout)(layout/masks)(wafermacro-chip single chip)*3333多项目晶圆技术(MPW)Chip1Chip1Chip6Chip2Chip5Chip4Chip3$30 000$30 000$5 000*3434表1.5 射光所已开辟的的代工渠道和工艺*3535清华大学设计的电 路南通工学院设计的电 路东南大学射光所应用东南大学射光所应用MPW制作芯片情况制作芯片情况以多项目晶圆形式完成了以多项目晶圆形式完成了0.350.35微米微米CMOSCMOS、0.250.25微米微米CMOSCMOS、0.0.1818微米微米CMOSCMOS和砷化镓等工艺的和砷化镓等工艺的多批次共多批次共100100多种集成电路的设计、制造和测试。多种集成电路的设计、制造和测试。山东大学设计的电路*3636集成电路设计技术的内容集成电路设计技术的内容国内外可用生产线资源国内外可用生产线资源(工艺工艺,价格价格,服务服务)的的研究和开发研究和开发可用生产线工艺文件可用生产线工艺文件(Tech-files)Tech-files)的建立的建立元件库元件库(Cell-libraries)Cell-libraries)的开发的开发具有知识产权的单元电路、系统内核具有知识产权的单元电路、系统内核(IP-IP-cores)cores)功能模块的开发和利用功能模块的开发和利用系统芯片系统芯片(SoC)SoC)设计设计多项目晶圆的开发与工艺实现多项目晶圆的开发与工艺实现芯片测试系统和方法的研究芯片测试系统和方法的研究*3737Measurement System of Ultra-High-Speed ICsDC SupplierR&S10MHz-40 GHzSignal Source Agilent 83484AAgilent 86100A Cost:US$400 000Probe Station*38381.1 集成电路的发展1.2 集成电路设计流程及设计环境 1.3 集成电路制造途径1.4 集成电路设计知识范围集成电路设计知识范围*39391.4 集成电路设计需要的知识范围1)系统知识 计算机/通信/信息/控制等学科2)电路知识 模拟/数字/模数混合/RFIC/MMIC3)工具知识 任务和内容 相应的软件工具 SPICE/VHDL/Verilog HDL/System Verilog/System C Cadence/Synopsys/Mentor4)工艺知识 元器件特性和模型/工艺原理和过程*4040End