ICT测试原理及程式简介ppt课件

ICTICT測試原理及程式簡介測試原理及程式簡介EPDVIII ICTEPDVIII ICTRandy.xiangRandy.xiangICT測試原理及程式簡介EPDVIII ICT1一.ICT的功能 ICT也叫在線測試儀，是一台靜態元件測試儀，它能准確，高速地測量PCB上已裝元件的不良問題，包括元件的漏件，錯件，裝反，空焊，來料不良，PCB上金道之間的開短路等。可測元件包括：電阻，電容，二極管，三極管，電感，變壓器，IC等絕大多數電子元件。一.ICT的功能 ICT也叫在線測試儀，是一台靜態元件測試儀2二.ICT的硬件結構 ICT包括ICT系統主機，電腦系統，壓床，測試治具。其中ICT系統主機包括：電源部分，量測控制板，I/O卡，DC量測板，AC量測板，開關板，HP-JET量測板，高壓量測板(選配件)。二.ICT的硬件結構 ICT包括ICT系統主機，電腦系統，3公司公司:TRI(Test Research Inc.)德律科技德律科技產地產地:台灣台灣 工作條件工作條件治具類型治具類型:真空治具真空治具.真空壓力真空壓力:最小最小56cmHg.外部真空管外部真空管2根根.氣壓氣壓:4kg/cm2 6kg/cm2.氣壓管氣壓管1根根.操作溫度操作溫度:0。C 30。C.環境濕度環境濕度:25%RH-75%RH.最小工作空間最小工作空間:深：深：1.5 公尺。公尺。寬：寬：2.0 公尺。公尺。高：高：2.0 公尺。公尺。公司:TRI(Test Research Inc.)德律4TRI 8001測試畫面測試畫面TRI 8001測試畫面5公司公司:TRI(Test Research Inc.)德律科技德律科技產地產地:台灣台灣 工作條件工作條件電源電源:3 AC 220V-245V,50/60 Hz5%氣壓氣壓:46KGFCM2公司:TRI(Test Research Inc.)德律6TRI 518測試操作畫面測試操作畫面TRI 518測試操作畫面7相匹配的治具簡介相匹配的治具簡介8 相匹配的治具必需為真空治具相匹配的治具必需為真空治具,即治具下壓的即治具下壓的動力為真空動力為真空.真空治具根據繞線長度分為真空治具根據繞線長度分為:長線治長線治具具,短線治具和無線治具短線治具和無線治具.我們現在使用的治具為長線治具我們現在使用的治具為長線治具.治具內部結構如下治具內部結構如下:相匹配的治具必需為真空治具,即治具下壓的動力為真空9SENSOR壓棒SENSOR壓棒10探針彈簧密封墊探針彈簧密封墊11氣管氣管油壓撐竿油壓撐竿雙絞線繞線BUFFER BOARD氣管油壓撐竿雙絞線繞線BUFFER BOARD12InterfaceInterface13Introduction of Agilent 3070 Introduction of Agilent 3070 14Agilent 3070 Family307X,up to 5200 nodes327X,up to 1300 nodes317X,up to 2600 nodesAgilent 3070 Family307X,up to15Anatomy of the Agilent Medalist 3070Agilent 3070 Hardware Agilent 3070Electronics CabinetDUT power suppliesExternal InstrumentsTestheadFlat Screen Monitor on moveable arm.Keyboard on moveable arm.End Cabinet contains Computer,Power Distribution Unit,Testhead rotation switch.TestheadTest Fixture Emergency Power Off SwitchTest FixtureMother Board (one per bank)Module power SuppliesAnatomy of the Agilent Medalis16 Agilent3070 測試畫面測試畫面 Agilent3070 測試畫面17Anatomy of the Agilent Medalist i3070 FixtureProbe to Pin WiringTest ProbeSupport PlateProbe PlatePersonality PinAlignment PlatePrinted Circuit BoardFixture FrameVacuum GasketR1StimulusResponseAnatomy of the Agilent Medalis18Anatomy of the Agilent Medalist 3070Agilent 3070 TestHeadBank 2 Bank 1Module 2 Module 0Module 3 Module 1Slot 1Slot 1Slot 1Slot 1Slot 1:ASRUSlot 6:Module Control CardAll others:Pin CardsPin 78 -1Pin 1 -78Anatomy of the Agilent Medalis19Fixture NumberingBRC:Bank Row ColumnBank 2 Bank 1Module 2Module 3Module 0Module 1Slot 1:ASRUSlot 6:ControlSlot 1:ASRUSlot 6:ControlSlot 1:ASRUSlot 6:ControlSlot 1:ASRUSlot 6:ControlMOTHER BOARDMOTHER BOARDRow 1Row11Row 13Row 23Row 1Row11Row 13Row 23Column 78 1 78 11A at:2 20 61CLOCK_ENABLE at:2 18 48Double Density node at:2 20 1 61Bank 1 Node:1 18 48Fixture NumberingBRC:Bank Row20 Anatomy of the Agilent Medalist 3070 The Module Control Cards The Analog Stimulus-Response Unit(ASRU)Agilent 3070 ModuleMother cardASRU cardControl cardPin cardSlot 1Slot 2Slot 3Pin cardSlot 4Slot 8Slot 6Slot 7Slot 5Slot 9Slot 10Slot 11Pin cardPin cardPin cardPin cardPin cardPin cardPin cardModule card configuration Anatomy of the Agilent Med21ASRU Card提供模拟激励信号使用测量运算放大器进行反馈信号的测量 提供上电测试的电源通道配在每个模块第1号插槽 ASRU Card提供模拟激励信号22Module Control Card控制实际的测试过程 2个rcvc,测试频率带有8个通用开关(GP Relay)配在每个模块的第 6 号插槽Module Control Card控制实际的测试过程 23 MUX S I A B L GMOADetectorAuxSourceHybrid Double DensityChannel AChannel B.Channel HPin CardX1.X8 XG XLAnalog SubsystemDigital Subsystem9:2R1ASRU MUX S I A B 24Hybrid 32 CardChannel 0Channel 8.6:2Pin CardX1.X8 XG XLDigital Subsystem3:2 MUX S I A B L GMOADetectorAuxSourceAnalog SubsystemASRUHybrid 32 CardChannel 0Channel25ICT TEST程式程式与夾具与夾具命名規則1.ICT程式命名規則程式命名規則 設備型號設備型號T(TR8001,TR518),A(Agilent 3070)T,A+P/N+EC+夾具套數夾具套數 2.ICT夾具命名規則夾具命名規則 設備型號設備型號T,A+P/N+夾具套數夾具套數ICT TEST程式与夾具命名規則1.ICT程式命名規則26MHS机种为例：P/N：69Y4784 EC:N31078RICT程式命名程式命名:A90Y4784N31078R_01ICT程式命名程式命名:A90Y4784_01MHS机种为例：P/N：69Y4784 EC:N310727三.ICT的基本測試原理1.隔離量測原理 ICT其實是一台高級的萬用表，但它具有隔離(GUARDING)功能，這是它不同于萬用表的最大特點。GUARDING的作用是使一個被測元件在測試時不受旁路元件的影響，而萬用表做不到這一點。在 ICT 內部電路中利用一顆 OP放大器 當做一個隔離點（最多可有五個隔離點），如果是:三.ICT的基本測試原理1.隔離量測原理28source:http:/ Overview of 3070 TestUnpoweredTestsShorts Analog IncircuitVTEP/TestJetPoweredTestsSetup PowerSuppliesDigital IncircuitAnalog PoweredPinsOther PoweredAn Overview of 3070 TestUnpowe30Part 3 Pins TestPart 3 Pins Test31Pins测试概述ICT测试的原理要求夹具的探针和电路板的测试点(testpad)要有良好的电气接触.Pins测试就是在测试正式开始前验证探针和测试点有无有无接触的工序.Pins测试只定性验证有无接触，pins pass是最低要求，并不能保证接触良好.(绕线出现错误；pins接触不好，阻抗大，但依然有current flow;隔离点无法 测)Pins测试概述ICT测试的原理要求夹具的探针和电路板的测试32Pins Test“A”“B”“C”“D”“E”“F”“G”“Node_Names”+2.5V10KDVMSNode E has no current flow.It is capacitively isolated and cannot be tested in Pins Test.Pins Test“A”“B”“C”“D”“E”“F”“G”33Pins Test-Syntaxnodes Anodes Bnodes Cnodes D!nodes E”!node capacitively isolatednodes”Fnodes”GPins Test-Syntaxnodes Ano34Pins Test Called from testplanPins test的预定义 sub Set_Custom_Option global Off,Pretest,Failure！设置全局常量 global Chek_Point_Mode Chek_Point_Mode=Pretest !choose Off,Pretest,Failure ！选择pins测试模式，off不进行pins测试 ！pretest在其它测试前进行pins测试 ！failure其它测试fail后，进行pins测试end subPins Test Called from testplan35Pins测试的调试Pins测试中的节点排列顺序不影响测试结果Pins测试中没有其他测试选项所以pins测试只有node的取舍 哪些节点pins不可测?p电容阻隔的点（capacitively isolated）IPG自动注释p只连到IC的NC脚的 IPG自动注释p所连器件在板上都没有放(no pop)的 手动确认Pins测试的调试Pins测试中的节点排列顺序不影响测试结果36Part 4Shorts Test&Opens Test L201L201-1L201-2100 ohmsDVM0.1VPart 4Shorts Test&Opens Test37Shorts Test overviewShorts Test overview38Shorts Test!IPG:rev B.03.60 threshold 12settling delay 50.00usettling delay 525.0ushort“L201-1”to“L201-2”settling delay 50.00ushort“J201-1”to“J201-2”.threshold 1000.nodes“Data7”nodes“R201-2”nodes“R201-1”.threshold 8.nodes“R202-2”nodes“R202-1”nodes“GND”DVML201Series Resistance=6ohmsR202 at 33ohmsDVMR201 at 20kL201-1L201-2R201-1R201-2R202-1R202-2Shorts Test!IPG:rev B.03.60 39Expected ShortsL201L201-1L201-2100 ohmsDVM0.1V如图，对L201 进行shorts测试，预期为短路。a).设置阀值为12欧姆，如果R测量12(threshold)，则测试pass，反之，fail。b).设置从加信号到开始测量的延时，以致等待信号稳定。c).测量两个节点之间的阻值，并判断！语法如下：!In the“shorts”file!Syntax!short“Node_1”to“Node_2”!threshold 12Settling delay 50uSettling delay 525uShorts“L201-1”to“L201-2 Expected ShortsL201L201-1L201-40Shorts Test(Good Board)Testing For Shorts100mV100 W“A”“B”“C”“D”“E”“F”“G”“Node_Names”Shorts Test(Good Board)Testi41Shorts Test(Bad Board)Testing For Shorts100mV100 W“A”“B”“C”“D”“E”“F”“G”?Which node is shorted to node C?A short has been detected from node C to one of the remaining nodes D,E,F or GShorts Test(Bad Board)Testin42Shorts Test(Bad Board)Testing For Shorts100mV100 W“A”“B”“C”“D”“E”“F”“G”?Which node is shorted to node C?A short has been detected from node C to one of the remaining nodes D,E,F or GNode C is not shorted to nodes D and ENode C is shorted to either nodes F or GNode C may be shorted to node GThis is not assumed!Node C is shorted to node GShorts Test(Bad Board)Testin43假象短路的调试假象短路出现的原因是特定的节点的测试顺序造成误判,必须在程序发布前排除方法是将出错的节点（或者节点群）挪到被短路的节点(或节点群）后面。这个过程在调试中可能要重复几次,挪动时最好在同一个threshold设置群之内.可以自己设置threshold，但是要遵循threshold值从大到小的顺序,Threshold最低尽量不要设到4以下，尤其是电源点。否则会有漏掉真正短路的可能.不要轻易把节点放到测试文件的末尾，这样可能造成开短路 覆盖率的缺失，尤其是电源点或者VCC这类本身就是低阻抗的节点.调试时settling delay可以加的比较大，在优化时再减小假象短路的调试假象短路出现的原因是特定的节点的测试顺序造成误44Shorts Test-Report Optionsreport common devicesreport limit 12Short#1From:D3 22044To:D4 21938Common Devices:U1 U4 report netlist,common devicesreport limit 12Short#1From:D3 22044 u1.5 u4.3 u5.2 u7.5To:D4 21938 u1.8 u4.4 u6.2 u2.10 Common Devices:u1 u4report phantomsShort#1From:D3 22044To:D4 21938Shorts Test-Report Optionsre45Part 5Analog TestcapacitorsconnectorsdiodesFETsfusesinductorsjumpersresistorsswitchestransistorszenersPart 5Analog Test46Part 6 Testjet&VTEP&iVTEPPart 6 Testjet&VTEP&47The VTEP/iVTEP/TestJet TestBGA with floating metal tops/heat spreaders are testable!PCBAC SignalGroundVTEP Sensor plate C measuredElectronics board(Amplifier)To MultiplexCardMetal BGA Under-TestFloatingMetal TopThe VTEP/iVTEP/TestJet TestBGA48TestJet测试能力的极限值为20fF，VTEP测试能力的极限值为5fF。低于5的值使用iVTEP来进行测试，但是iVTEP的测试速度比较慢，而且不能用来测试连接器。Bar=Num Pins in Range051015202530 0 to 5 5 to 10 10 to 15 15 to 20 20 to 25 25 to 30 30 to 35 35 to 40 40 to 45 45 to 50TestJet limitMeasurement(in fF)VTEP limit1.27 mm pitch593 Solder Balls0.8mm pitch1202 SBTestJET和VTEP的测试界限Aug,2010TestJet测试能力的极限值为20fF，VTEP测试能力的49The VTEP/TestJet VerificationThe VTEP/TestJet Verification50The TestJet Testdefault threshold low 20 high 10000device“u1”test pins 1 test pins 2,3 test pins 4,5,6 !test pins 7 !Ground pins commented by IPG test pins 8 test pins 13 !test pins 14 !Fixed pins commented by IPGdevice“u2”bottom;test pins 1 test pins 2 .The TestJet Testdefault thresh51Turn On AutoDebug for iVTEP+VTEPTurn On AutoDebug for iVTEP+52AutoDebug calculates the threshold limit Before ADBAfter ADBAutoDebug calculates the thres53The TestJet Test-After Debugdefault threshold low 20 high 10000device“u1”;threshold low 15 high 10000 test pins 1 test pins 2,3;threshold low 350 high 10000 test pins 4,5,6;threshold low 450 high 10000 !test pins 7 !Ground pins commented by IPG test pins 8 !test pins 13 !Test measures 9 test pins 8 test pins 14 !Fixed pins commented by IPGdevice“u2”bottom;test pins 1;threshold low 15 high 10000 test pins 2 test pins 3;threshold low 40 High 10000 .The TestJet Test-After Debug54Part 10 Overview of Boundary-ScanTest DataIn(TDI)Test DataOut(TDO)Part 10 Overview of Boundary-S55Typical IC with Boundary-ScanBoundaryCellsCoreLogicTest DataIn(TDI)Test DataOut(TDO)Test ModeSelect(TMS)Test Clock(TCK)TEST ACCESS PORT CONTROLLER(TAP)The device can be controlledand tested through TDI,TCK,TMS,&TDOArrows denote access pointsTypical IC with Boundary-ScanB56Basic Test of IC with Boundary-ScanTest DataIn(TDI)Test DataOut(TDO)lDo not need to understand the Device Function(Core Logic)lScan data in TDI to Output cells.Tester verifies data on outputs.lTester applies Data on inputs.Cellscapture data on inputs.Datascanned out TDO for verification.Basic Test of IC with Boundary57The Boundary-Scan Test Development Processl Start with the BSDL file BSDL means Boundary-Scan Description Language”A language for describing the device specific characteristics of 1149.1 devices Language subset of VHDLl Who will write BSDL ASIC designers Semiconductor vendors Test engineersThe Boundary-Scan Test Develop58Typical IC with Boundary-ScanTest DataIn(TDI)CoreLogicTMS=SerialTest Clock(TCK)TEST ACCESS PORT CONTROLLER(TAP)010101010101101010010101010101TMS=ParallelTypical IC with Boundary-ScanT59TMS=ParallelTypical IC with Boundary-ScanTest DataIn(TDI)CoreLogicTMS=SerialTest Clock(TCK)TEST ACCESS PORT CONTROLLER(TAP)010101010101101010101010TMS=ParallelTypical IC with 60 Thank you!&More Questions?Thank you!61