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SystemVerilogHistoryn nEnhancement of Verilogn n2002 accellera publishes SystemVerilog 3.0n n2004-accellera publishes SystemVerilog 3.1an n 2005 IEEE standardizes SystemVerilogWhats in itn nVerilogn nModeling:n nNew constructsNew constructsn nSynthesizable Synthesizable n nVerification:n nTestbench automationTestbench automationn nAssertionsAssertionsSV for Modelingn nVerilogVerilogn nInterfacesInterfacesn nData types:2 and 4 levels,int,shortint,longint,Data types:2 and 4 levels,int,shortint,longint,byte,logic,typedefbyte,logic,typedefn n2-state modeling2-state modelingn nFlow control mechanisms:Break,continue,Flow control mechanisms:Break,continue,return,return,n nCastingCastingn nAnd much more.And much more.SV for Verificationn nGeneration:Constrained random generation Generation:Constrained random generation n nCheck:AssertionsCheck:Assertionsn nCoverageCoveragen nSemaphoresSemaphoresn nTest program blocksTest program blocksn nClassesClassesn nInheritanceInheritancen nAnd much more And much more SV for Verificationn nGeneration:Constrained random generation Generation:Constrained random generation n nCheck:AssertionsCheck:Assertionsn nCoverageCoveragen nSemaphoresSemaphoresn nTest program blocksTest program blocksn nClassesClassesn nInheritanceInheritancen nAnd much more And much more Constrained Random Generationn nWithin classWithin classn nFields should be declared as randomFields should be declared as randomclass packet;class packet;randc bit7:0 addr;randc bit7:0 addr;rand bit7:0 data;rand bit7:0 data;constraint legal_pkt constraint legal_pkt addr=2;addr=2;endclassendclassInterfacen nSeparate communication from functionalityn nA bundle of wires that simplifies hierarchical connectionsn nThe block uses an interfaceAvailable Toolsn nTrainingn nConsultingn nSimulatorsn nSVA packagesn nMethodologyn nSynopsis,Mentor,Cadence Synopsis,Mentor,Cadence n nEverybody has somethingSo?n nGood new capabilitiesGood new capabilitiesn nModeling and Modeling and verification in same verification in same languagelanguagen nApparently all Apparently all verification servicesverification servicesn nSuitable for Suitable for designers?designers?n nSynthesizableSynthesizablen nComplicated to learnComplicated to learnn nImmature toolsImmature toolsn nImmature Immature methodologymethodologyn nNo experience No experience
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