veriloghdl-电子琴课程设计.doc

湖北文理学院课程设计报告 题 目 Verilog hdl课程设计专 业 1211自动化 学生姓名 一天虹影 指导教师 单鸣雷 完成时间 201519 课程设计（报告）任务书（理 工 科 类）课程设计（报告）题目：电子琴的设计课程设计（论文）工作内容一、课程设计目标 1、培养综合运用知识和独立开展实践创新的能力；2、深入学习Verilog HDL，了解其编程环境；3、学会运用Modelsim和Quartus II等编程仿真软件；4、将硬件语言编程与硬件实物功能演示相结合，加深理解Verilog HDL的学习；二、研究方法及手段应用1、将任务分成若干模块，查阅相关论文资料，分模块调试和完成任务；2、遇到问题小组成员及时讨论得出解决方法；3、遇到本组内解决不了的问题，及时和其他小组交流或询问老师；4、程序仿真，仿真无问题后进行模块调试，根据实验箱上的硬件实现是否符合要求来检验程序正确与否。三、课程设计预期效果1、完成实验环境搭建；2、具有手动弹奏和自动播放功能；3、以按键（或开关）作为琴键，至少可以通过蜂鸣器输出7个音阶；4、自动播放曲目至少两首； 摘 要简易电子琴的设计通过通过软硬件结合实现，硬件系统包括主控器芯片、9个按键、LED、蜂鸣器等，软件资源包括编写Verilog HDL程序的应用软件Modelsim和仿真软件Quartus II。电子琴有按键代替琴键的弹奏功能和自动播放功能。按键有七个音，自动播放功能中有三首曲子，分别是两只老虎、天空之城和康定情歌。程序共有五个模块，分别为主模块、琴键模块、曲1模块、曲2模块、曲3模块。硬件实现是用三个LED灯组合亮暗分别表示七个按键按下情况，另外两个按键用来选择曲目。实验箱原始时钟为50MHz，分频后变成不同的频率输出，通过蜂鸣器输出不同频率的声音。音乐的节拍通过分频变为4Hz，作为1/4拍。通过主模块调用各模块实现电子琴的功能。【关键词】Verilog HDL 电子琴 模块 分频ABSTRACTThis article introduced the simple electric pianos design. It realizes through the software and hardware union. The hardware system includes a director, 9 keys, LEDs and a buzzer. The software design uses Verilog HDL. Emulation uses Quartus II. It can broadcast the system establishment the corresponding note, and can complete a military song the broadcast, but also has shows the sound the function. Designs the simple electric piano to have in the hardware. The program has seven modules, including main module, fractional frequency module and so on. Keyboard with keys to play the function and replace the keys to play function. Key has seven sound, automatic playback function with three in song, were the two tiger , the sky city and kangding love songs. Software has its merit. It is perfect in the software Verilog HDL. The original frequency is divided into different frequencys. The piano makes sound by the buzzer with different frequencys.【keywords】Verilog HDL electric piano module fractional frequency第一章 系统设计第一节 课题目标及总体方案本次项目设计课程的目标是让我们在学习Verilog HDL的基础上更加深入的理解硬件设计语言的功能、作用及其特征，并且将我们的动手能力与创新能力结合起来。本次电子琴实验的目标是：1、具有手动弹奏和自动播放功能；2、以按键（或开关）作为琴键，至少可以通过蜂鸣器输出7个音阶；3、自动播放曲目至少两首；本次实验的方框图为：（每个模块中都有分频）主模块九个键Key1到Key7用于弹奏Key8与Key9（mm）用于选择歌曲mm=00按键模块Key1到Key7模块名digital_pianomm=01曲目1两只老虎模块名 bellmm=10曲目2康定情歌模块名 bell2mm=11曲目3天空之城模块名 bell3第二节 设计框图说明 一、 主模块主模块中用mm=(key8,key9)值的不同选择调用不同模块，mm=01调用曲目1模块，即bell模块；mm=10调用曲目2模块，即bell2模块；mm=11调用曲目3模块，即bell3模块；而在key8与key9没有被按下的情况下，程序调用按键模块，即digital_piano模块module main(inclk,outclk,key1,key2,key3,key4,key5,key6,key7,key8,key9,num);input inclk;input key1,key2,key3,key4,key5,key6,key7,key8,key9;output outclk;output3:0num;reg outclk,clk_6M;reg 3:0c;wire out1,out2,out3,out4;wire8:0 key;reg 1:0mm;assign key = key1,key2,key3,key4,key5,key6,key7,key8,key9; /由按键拼键为变量key /调用子调块digital_piano m1(.inclk(inclk),.key1(key1),.key2(key2),.key3(key3),.key4(key4), .key5(key5),.key6(key6),.key7(key7),.beep2(out2),.num(num); bell m2(.inclk(inclk),.beep1(out1);bell2 m3(.inclk(inclk),.beep3(out3);bell3 m4(.inclk(inclk),.beep4(out4);always (posedge clk_6M) /在时钟的上升沿检测是否有按键按下beginif(key = 9b111111110)mm = 2b01;else if(key=9b111111101)mm = 2b10;else if(key=9b111111100)mm = 2b11;else mm = 2b00;end always(posedge inclk) begin if(c4d4) c=c+4d1; else begin c=4d0; clk_6M=clk_6M; endend always (posedge clk_6M) beginif(mm = 2b01)outclk = out1;else if(mm = 2b00)outclk = out2;else if(mm = 2b10)outclk = out3;else outclk = out4;endendmodule二、按键模块Key1到key7对应do到si七个音，用于模拟电子琴弹奏/digital_piano子模块module digital_piano(inclk,key1,key2,key3,key4,key5,key6,key7,beep2,num);input inclk,key1,key2,key3,key4,key5,key6,key7;output3:0num;output beep2; wire 6:0 key_code;reg 3:0c;reg clk_6M; reg beep_r;reg 3:0num;reg 15:0 count;reg 15:0 count_end;parameter Do = 7b1111110, /状态机的7个编码，分别对应中音的7个音符 re = 7b1111101, mi = 7b1111011, fa = 7b1110111, so = 7b1101111, la = 7b1011111, si = 7b0111111;assign key_code = key7,key6,key5,key4,key3,key2,key1;assign beep2 = beep_r; /输出音乐always(posedge inclk) begin if(c4d4) c=c+4d1; else begin c=4d0; clk_6M=clk_6M; endendalways(posedge clk_6M) /分频模块，得出乐谱begincount = count + 16d1; /计数器加1if(count = count_end)begincount =16d0; /计数器清零beep_r = !beep_r; endendalways(posedge clk_6M) /状态机，根据按键状态，选择不同的音符输出begincase(key_code)Do: count_end = 16d11450;re: count_end = 16d10204;mi: count_end = 16d09090;fa: count_end = 16d08571;so: count_end = 16d07802;la: count_end = 16d06802;si: count_end = 16d06060;default:count_end = 16d0;endcaseend always (posedge clk_6M)begincase(key_code)Do: num=4b0001;re:num=4b0010;mi: num=4b0011;fa: num=4b0100;so: num=4b0101;la: num=4b0110;si: num=4b0111;endcaseendendmodule二、 曲目1模块/bell子模块 两只老虎module bell (inclk,beep1);input inclk; /系统时钟output beep1; /蜂鸣器输出端reg 3:0high,med,low;reg 15:0origin;reg beep_r; /寄存器reg 7:0state; reg 15:0count;assign beep1=beep_r; /输出音乐/时钟频率6MHzreg clk_6MHz;reg 2:0 cnt1; always(posedge inclk)begin if(cnt13d4) cnt1=cnt1+3b1; else begin cnt1=3b0; clk_6MHz=clk_6MHz; endend/时钟频率4MHzreg clk_4Hz;reg 24:0 cnt2; always(posedge inclk)begin if(cnt225d6250000) cnt2=cnt2+25b1; else begin cnt2=25b0; clk_4Hz=clk_4Hz; endendalways (posedge clk_6MHz)begincount = count + 1b1; /计数器加1if(count = origin)begincount = 16h0; /计数器清零beep_r = !beep_r; /输出取反endendalways(posedge clk_4Hz)begincase(high,med,low)12b000000010000:origin=11466;/mid112b000000100000:origin=10216;/mid212b000000110000:origin=9101;/mid312b000001000000:origin=8590;/mid412b000001010000:origin=7653;/mid512b000001100000:origin=6818;/mid612b000000000101:origin=14447;/low5endcaseendalways (posedge clk_4Hz)/歌曲beginif(state =63) state = 0;/计时，以实现循环演奏elsestate = state + 1;case(state)0,1: high,med,low=12b000000010000;/mid12,3:high,med,low=12b000000100000;/mid24,5:high,med,low=12b000000110000;/mid36,7:high,med,low=12b000000010000;/mid18,9: high,med,low=12b000000010000;/mid110,11:high,med,low=12b000000100000;/mid212,13:high,med,low=12b000000110000;/mid314,15:high,med,low=12b000000010000;/mid116,17:high,med,low=12b000000110000;/mid318,19: high,med,low=12b000001000000;/mid420,21,22,23: high,med,low=12b000001010000;/mid524,25:high,med,low=12b000000110000;/mid326,27: high,med,low=12b000001000000;/mid428,29,30,31: high,med,low=12b000001010000;/mid532:high,med,low=12b000001010000;/mid533: high,med,low=12b000001100000;/mid634:high,med,low=12b000001010000;/mid535:high,med,low=12b000001000000;/mid436,37:high,med,low=12b000000110000;/mid338,39:high,med,low=12b000000010000;/mid140:high,med,low=12b000001010000;/mid541: high,med,low=12b000001100000;/mid642:high,med,low=12b000001010000;/mid543:high,med,low=12b000001000000;/mid444,45:high,med,low=12b000000110000;/mid346,47:high,med,low=12b000000010000;/mid148,49:high,med,low=12b000000100000;/mid250,51:high,med,low=12b000000000101;/low552,53,54,55:high,med,low=12b000000010000;/mid156,56:high,med,low=12b000000100000;/mid257,58:high,med,low=12b000000000101;/low559,60,61,62,63:high,med,low=12b000000010000;/mid1default : high,med,low=12bx;endcaseendendmodule三、 曲目2模块/bell2子模块康定情歌module bell2 (inclk,beep3);input inclk; /系统时钟output beep3; /蜂鸣器输出端reg 3:0high,med,low;reg 15:0origin;reg beep_r; /寄存器reg 7:0state; reg 15:0count;assign beep3=beep_r; /输出音乐/时钟频率6MHzreg clk_6MHz;reg 2:0 cnt1; always(posedge inclk)begin if(cnt13d4) cnt1=cnt1+3b1; else begin cnt1=3b0; clk_6MHz=clk_6MHz; endend/时钟频率4MHzreg clk_4Hz;reg 24:0 cnt2; always(posedge inclk)begin if(cnt225d6250000) cnt2=cnt2+25b1; else begin cnt2=25b0; clk_4Hz=clk_4Hz; endendalways (posedge clk_6MHz)begincount = count + 1b1; /计数器加1if(count = origin)begincount = 16h0; /计数器清零beep_r = !beep_r; /输出取反endendalways(posedge clk_4Hz)begincase(high,med,low) b000000000001:origin=22900; /低1 b000000000010:origin=20408; /低2 b000000000011:origin=18181; /低3 b000000000101:origin=15267; /低5b000000000110:origin=13605; /低6b000000000111:origin=11472; /中1b000000100000:origin=10216; /中2b000000110000:origin=9101; /中3b000001010000:origin=7653; /中5b000001100000:origin=6818; /中6b000100000000:origin=5733; /高1b001000000000:origin=5108; /高2b001100000000:origin=4551; /高3endcaseendalways (posedge clk_4Hz)beginif(state =103) state = 0;elsestate = state + 1; /康定情歌case(state)0,1: high,med,low=b000000110000;/中32,3: high,med,low=b000001010000;/中54,5: high,med,low=b000001100000;/中66: high,med,low=b000001100000;/中67: high,med,low=b000001010000;/中58,9,10: high,med,low=b000001100000;/中611: high,med,low=b000000110000;/中312,13,14,15: high,med,low=b000000100000;/中216,17: high,med,low=b000000110000;/中318,19: high,med,low=b000001010000;/中520,21: high,med,low=b000001100000;/中622: high,med,low=b000001100000;/中623: high,med,low=b000001010000;/中524,25: high,med,low=b000001100000;/中626,27,28,29,30,31:high,med,low=b000000110000;/中332,33: high,med,low=b000000110000;/中334,35: high,med,low=b000001010000;/中536,37: high,med,low=b000001100000;/中638: high,med,low=b000001100000;/中639: high,med,low=b000001010000;/中540,41,42: high,med,low=b000001100000;/中643: high,med,low=b000000110000;/中344,45,46,47: high,med,low=b000000100000;/中248,49: high,med,low=b000000000101;/中550,51: high,med,low=b000000110000;/中352: high,med,low=b000000100000;/中253: high,med,low=b000000110000;/中354: high,med,low=b000000100000;/中255: high,med,low=b000000000111;/156,57: high,med,low=b000000100000;/中258,59,60,61,62,63:high,med,low=b000000000110;/低664,65: high,med,low=b000001100000;/中6 66,67,68,69,70,71:high,med,low=b000000100000;/中272,73: high,med,low=b000000000101;/中574,75,76,77,78,79:high,med,low=b000000110000;/中380: high,med,low=b000000100000;/中281: high,med,low=b000000000111;/182,83,84,85,86,87:high,med,low=b000001100000;/中688,89: high,med,low=b000000000101;/中590,91: high,med,low=b000000110000;/中392: high,med,low=b000000100000;/中293: high,med,low=b000000110000;/中394: high,med,low=b000000100000;/中295: high,med,low=b000000000111;/196,97: high,med,low=b000000100000;/中298,99,100,101,102,103:high,med,low=b000001100000;/中6endcaseendendmodule四、 曲目3模块/bell3子模块天空之城module bell3 (inclk,beep4);input inclk; /系统时钟output beep4; /蜂鸣器输出端reg 3:0high,med,low;reg 15:0origin;reg beep_r; /寄存器reg 7:0state; reg 15:0count;assign beep4=beep_r; /输出音乐/时钟频率6MHzreg clk_6MHz;reg 2:0 cnt1; always(posedge inclk)begin if(cnt13d4) cnt1=cnt1+3b1; else begin cnt1=3b0; clk_6MHz=clk_6MHz; endend/时钟频率4MHzreg clk_4Hz;reg 24:0 cnt2; always(posedge inclk)begin if(cnt225d6250000) cnt2=cnt2+25b1; else begin cnt2=25b0; clk_4Hz=clk_4Hz; endendalways (posedge clk_6MHz)begincount = count + 1b1; /计数器加1if(count = origin)begincount = 16h0; /计数器清零beep_r = !beep_r; /输出取反endendalways(posedge clk_4Hz)begincase(high,med,low) b000000000001:origin=22900; /低1 b000000000010:origin=20408; /低2 b000000000011:origin=18181; /低3 b000000000100:origin=17142; /低4b000000000101:origin=15267; /低5b000000000110:origin=13605; /低6b000000000111:origin=12121; /低7b000000000111:origin=11472; /中1b000000100000:origin=10216; /中2b000000110000:origin=9101; /中3b000000111000:origin=8571; /中4b000001010000:origin=7653; /中5b000001100000:origin=6818; /中6b000010000000:origin=6060; /中7b000100000000:origin=5733; /高1b001000000000:origin=5108; /高2b001100000000:origin=4551; /高3b001010000000:origin=4294; /高4b010000000000:origin=3826; /高5b011000000000:origin=3409; /高6b010100000000:origin=3050; /高7endcaseendalways (posedge clk_4Hz)beginif(state =195)state = 0;elsestate = state + 1; /kang ding qing gecase(state)0:high,med,low=b000001100000;/中61: high,med,low=b000010000000;/中72,3,4:high,med,low=b000100000000;/高15:high,med,low=b000010000000;/中76,7: high,med,low=b000100000000;/高18,9:high,med,low=b001100000000;/高310,11,12,13,14,15: high,med,low=b000010000000;/中716,17: high,med,low=b000000110000;/中318,19,20:high,med,low=b000001100000;/中621: high,med,low=b000001010000;/中522,23: high,med,low=b000001100000;/中624,25:high,med,low=b000000000111;/中126,27,28,29,30,31: high,med,low=b000001010000;/中5 32: high,med,low=b000000110000;/中333: high,med,low=b000000110000;/中334,35,36:high,med,low=b000000111000;/中437: high,med,low=b000000110000;/中338: high,med,low=b000000111000;/中439,40,41:high,med,low=b000100000000;/高142,43,44: high,med,low=b000000110000;/中345,46,47:high,med,low=b000100000000;/高148,49,50:high,med,low=b000010000000;/中751,52,53: high,med,low=b000000111000;/中454,55,56,57,58,59,60,61: high,med,low=b000010000000;/中762:high,med,low=b000001100000;/中663: high,med,low=b000010000000;/中764,65,66:high,med,low=b000100000000;/高167:high,med,low=b010100000000;/高768,69:high,med,low=b000100000000;/高170,71:high,med,low=b001100000000;/高372,73,74:high,med,low=b000010000000;/中775,76:high,med,low=b000000110000;/中3 77,78,79: high,med,low=b000001100000;/中680:high,med,low=b000000000101;/中581,82:high,med,low=b000001100000;/中683,84: high,med,low=b000000000111;/中185,86,87,88,89,90: high,med,low=b000001010000;/中5 91: high,med,low=b000000110000;/中392: high,med,low=b000000110000;/中393,94:high,med,low=b000000111000;/中4 95:high,med,low=b000100000000;/高196,97,98:high,med,low=b000010000000;/中799,100:high,med,low=b000100000000;/高1101,102:high,med,low=b001000000000;/高2103:high,med,low=b001100000000;/高3104,105,106,107,108,109:high,med,low=b000100000000;/高1110: high,med,low=b000010000000;/中7111,112:high,med,low=b000001100000;/中6113,114:high,med,low=b000010000000;/中7115,116:high,med,low=b000001010000;/中5117,118,119,120,121,122:high,med,low=b000001100000;/中6123,124:high,med,low=b000000000111;/中1125:high,med,low=b001000000000;/高2 126,127,128: high,med,low=b001100000000;/高3129:high,med,low=b001000000000;/高2130,131:high,med,low=b001100000000;/高3132,133: high,med,low=b010000000000;/高5134,135,136,137,138,139:high,med,low=b001000000000;/高2140,141:high,med,low=b000001010000;/中5142,143,144: high,med,low=b000100000000;/高1145:high,med,low=b000010000000;/中7146,147:high,med,low=b000100000000;/高1148,149,150,151,152,153,154,155:high,med,low=b001100000000;/高3 156,157:high,med,low=b000001100000;/中6158,159:high,med,low=b000010000000;/中7160,161,162,163:high,med,low=b000100000000;/高1164,165:high,med,low=b000010000000;/中7166,167:high,med,low=b000100000000;/高1168,169:high,med,low=b001000000000;/高2170,171,172:high,med,low=b000100000000;/高1173,174,175,176,177,178:high,med,low=b000001010000;/中5179,180:high,med,low=b001010000000;/高4181,182:high,med,low=b001100000000;/高3183,184,185:high,med,low=b001000000000;/高2186,187:high,med,low=b000100000000;/高1188,189,190,191,192,193,194,195:high,med,low=b001100000000;/高3 endcaseendendmodule第二章 结果与讨论第二节 调试结果与问题分析 实验时我们使用了ModelSim编译软件，初写时编译出许多的错误，如端口的属性定义错误，语法上的错误等。 在硬件调试时，发现蜂鸣器的发出的七个基本音很不标准，细看程序是发现我们把分频数扩大了一倍，导致音调不准确，后改正之后，蜂鸣器的发声基本标准。 在进行管口连接时，管口部分设置颠倒，key1到key7发音顺序错误，不是按do、re、mi、fa、so、la、si的顺序发音。心得体会其实在此次试验中老师还指出了我们程序中的许多不足之处，例如：程序中一些时序问题，还有程序并行的问题等等。另外由于本次实验要用quartusII软件，对软件不熟悉导致了许多错误和问题的发生。通过这次实验，我不但熟悉了quartusII软件，也了解了开发的最基本流程和方法，也进一步加深了对Verilog编程语言的理解。在此次硬件课设的过程中，我们越来越认识到一点，编程对项目实现有着至关重要的，我们在硬件开发的过程中更应该重视编程，将编程看作是完善开发的不可缺少的一部分。在一次次的反复设计、论证和测试中，提高了逻辑分析能力、全面分析问题的能力以及发现问题、解决问题的能力。虽然设计过程非常烦琐，但这也磨练了我的意志。通过对各方面资料的收集，我的知识面也进一步拓宽了。同时，我也发现了自己的不足，像语言表达还比较差，不能更清楚地表达自己的意思，逻辑分析能力虽有提高，但还不够，编程能力还不足，有些预先的想法都未能实现。但发现问题也是好事，能使我们在这些方面多努力，加以改进。在系统的结构设计上也还有很长的路需要走，这是需要时间去积累的。在硬件仿真过程中我还明白了团队合作的重要性，有时候一个人一旦遇到困难的时候可能需要很多时间才能