静态时序分析基本原理和时序分析模型.ppt

Quartus IISoftwareDesignSeries TimingAnalysis Timinganalysisbasics 2 Objectives Displayacompleteunderstandingoftiminganalysis 3 Howdoestimingverificationwork Everydevicepathindesignmustbeanalyzedwithrespecttotimingspecifications requirementsCatchtiming relatederrorsfasterandeasierthangate levelsimulation boardtestingDesignermustentertimingrequirements exceptionsUsedtoguidefitterduringplacement routingUsedtocompareagainstactualresults IN CLK OUT combinationaldelays CLR 4 TimingAnalysisBasics Launchvs latchedgesSetup holdtimesData clockarrivaltimeDatarequiredtimeSetup holdslackanalysisI OanalysisRecovery removalTimingmodels 5 Path AnalysisTypes ThreetypesofPaths ClockPathsDataPathAsynchronousPaths ClockPaths AsyncPath DataPath AsyncPath TwotypesofAnalysis Synchronous clock datapathsAsynchronous clock asyncpaths Asynchronousreferstosignalsfeedingtheasynchronouscontrolportsoftheregisters 6 Launch LatchEdges CLK LaunchEdge LatchEdge DataValid DATA LaunchEdge theedgewhich launches thedatafromsourceregisterLatchEdge theedgewhich latches thedataatdestinationregister withrespecttothelaunchedge selectedbytiminganalyzer typically1cycle 7 Setup Hold Setup TheminimumtimedatasignalmustbestableBEFOREclockedgeHold TheminimumtimedatasignalmustbestableAFTERclockedge Valid DATA CLK DATA Together thesetuptimeandholdtimeformaDataRequiredWindow thetimearoundaclockedgeinwhichdatamustbestable 8 DataArrivalTime DataArrivalTime launchedge Tclk1 Tco Tdata CLK LaunchEdge Thetimefordatatoarriveatdestinationregister sDinput Comb Logic 9 ClockArrivalTime ClockArrivalTime latchedge Tclk2 CLK LatchEdge Thetimeforclocktoarriveatdestinationregister sclockinput Comb Logic 10 DataRequiredTime Setup DataRequiredTime ClockArrivalTime Tsu SetupUncertainty CLK LatchEdge Theminimumtimerequiredforthedatatogetlatchedintothedestinationregister Datamustbevalidhere Comb Logic 11 DataRequiredTime Hold DataRequiredTime ClockArrivalTime Th HoldUncertainty CLK LatchEdge Theminimumtimerequiredforthedatatogetlatchedintothedestinationregister Datamustremainvalidtohere Comb Logic 12 SetupSlack Themarginbywhichthesetuptimingrequirementismet Itensureslauncheddataarrivesintimetomeetthelatchingrequirement CLK LaunchEdge LatchEdge Comb Logic 13 SetupSlack cont d PositiveslackTimingrequirementmetNegativeslackTimingrequirementnotmet SetupSlack DataRequiredTime DataArrivalTime 14 HoldSlack Themarginbywhichtheholdtimingrequirementismet Itensureslatchdataisnotcorruptedbydatafromanotherlaunchedge CLK LatchEdge NextLaunchEdge Comb Logic 15 HoldSlack cont d PositiveslackTimingrequirementmetNegativeslackTimingrequirementnotmet HoldSlack DataArrivalTime DataRequiredTime 16 FPGA CPLDorASSP ASSPorFPGA CPLD I OAnalysis AnalyzingI OperformanceinasynchronousdesignusesthesameslackequationsMustincludeexternaldevice PCBtimingparameters CL Tdata Tclk1 Tclk2 OSC DataArrivalPath DataArrivalPath DataRequiredPath Representsdelayduetocapacitiveloading 17 Recovery Removal Recovery TheminimumtimeanasynchronoussignalmustbestableBEFOREclockedgeRemoval TheminimumtimeanasynchronoussignalmustbestableAFTERclockedge CLK ASYNC 18 Asynchronous Synchronous AsynchronouscontrolsignalsourceisassumedsynchronousSlackequationsstillapplydataarrivalpath asynchronouscontrolpathTsu Trec Th TremExternaldevice boardtimingparametersmaybeneeded Ex 1 ASSP FPGA CPLD OSC FPGA CPLD Example1 Example2 Dataarrivalpath Dataarrivalpath Datarequiredpath Datarequiredpath 19 WhyAreTheseCalculationsImportant CalculationsareimportantwhentimingviolationsoccurNeedtobeabletounderstandcauseofviolationExamplecausesDatapathtoolongRequirementtooshort incorrectanalysis Largeclockskewsignifyingagatedclock etc TimeQuesttiminganalyzerusesthemEquationstocalculateslackTerminology launchandlatchedges DataArrivalPath DataRequiredPath etc intimingreports 20 TimingModelsinDetail QuartusIIsoftwaremodelsdevicetimingattwoPVTconditionsbydefaultSlowCornerModelIndicatesslowestpossibleperformanceforanysinglepathTimingforslowestdeviceatmaximumoperatingtemperatureandVCCMINFastCornerModelIndicatesfastestpossibleperformanceforanysinglepathTimingforfastestdeviceatminimumoperatingtemperatureandVCCMAXWhytwocornertimingmodels EnsuresetuptimingismetinslowmodelEnsureholdtimingismetinfastmodelEssentialforsourcesynchronousinterfacesThirdmodel slow min temp availableonlyfor65nmandsmallertechnologydevices temperatureinversionphenomenon 21 GeneratingFast SlowNetlist SpecifyoneofthedefaulttimingmodelstobeusedwhencreatingyournetlistDefaultistheslowtimingnetlistTospecifyfasttimingnetlistUse fast modeloptionwithcreate timing netlistcommandChooseFastcornerinGUIwhenexecutingCreateTimingNetlistfromNetlistmenuCANNOTselectfastcornerfromTasksPane 22 SpecifyingOperatingConditions PerformtiminganalysisfordifferentdelaymodelswithoutrecreatingtheexistingtimingnetlistTakesprecedenceoveralreadygeneratednetlistRequiredforselectingslow min temp modelandothermodels industrial military etc dependingondeviceUseget available operating conditionstoseeavailableconditionsfortargetdevice ReferenceDocuments QuartusIIHandbook Volume3 Chapter7TheQuartusIITimeQuestTimingAnalyzer ReferenceDocuments SDCandTimeQuestAPIReferenceManual 25 OnlineTrainingWithAltera sonlinetrainingcourses youcan TakeacourseatanytimethatisconvenientforyouTakeacoursefromthecomfortofyourhomeoroffice noneedtotravelaswithinstructor ledcourses Eachonlinecoursewilltakeapproximateonetothreehourstocomplete LearnMoreThroughTechnicalTraining 26 AlteraTechnicalSupport ReferenceQuartusIIsoftwareon linehelpQuartusIIHandbookConsultAlteraapplications factoryapplicationsengineers MySupport