Cadence高速电路解决方案.ppt

Cadences Solution for High-Speed Design,Agenda,What is High-Speed Design? Ideal High-Speed Design Process Introduction to SPECCTRAQuest Power Integrity SPECCTRAQuest Demonstration,The Day of “High-Speed” Has Come,“Pc-board designers, meanwhile, were retooling in 1999 for high-speed design. Signal integrity, once confined to high-end boards, has become everybodys problem” Richard Goering, commenting on why the PCB layout market grew 20% while the IC layout market shrunk 30%, in EETimes 4/10/2000 page 70,Welcome Networking!,Hammerhead Networks,Agenda,What is High-Speed Design? Ideal High-Speed Design Process SPECCTRAQuest Demonstration Introduction to SPECCTRAQuest Power Integrity,NOW,What is “High-Speed” ?,Over 50 MHz is “High-Speed”,“High-Speed” isnt related to frequency, its a function of rise times,A net is “High-Speed” when its round-trip delay is greater than twice its edge-speed,A signal is “High-Speed” when it is faster than anything youve designed before,“High-Speed” occurs when skin effect and dielectric loss effects become important,Huh?,Question: Which is a “High-Speed” Problem?,Answer: They BOTH Are !,Definition of High-Speed,A net can be considered High-Speed when you have to do something other than simply connect it.,High-Speed Design Involves 2 Things,Nets that are understood, and must be constrained Nets that must be analyzed to be understood, and then constrained,Nets that are understood, and must be constrained Nets that must be analyzed to be understood, and then constrained,SDRAM DIMM Layout,MODELS,Datasheets,Front-side Bus Simulation,Most Tools Force You to Choose,Great Simulator!,Analyze,Constrain,Great Layout System!,Hmm.,But for High-Speed You Need BOTH,All in ONE integrated & interactive environment !,Lets Go!,SPECCTRAQuest: Integrated Constraint & Analysis,Model Development & Verification,Topology Entry & Floorplanning,Constraint Driven Layout,Analyze,Constrain,SPECCTRAQuest helps you manage the process of High-Speed PCB development through both Simulation Analysis & Constraint-Driven Layout tasks A Complete Solution!,Pre-Route Soln-Space Analysis,Expanding Existing Process,Physical Model Creation,Outline/ Floorplan/ Room Def/,Schematic Model Creation,Schematic Creation,SCHEMATIC,LAYOUT,To Final Verification,netlist,SI Clean Route,Back- Annotate,PCB Routing,Agenda,What is High-Speed Design? Ideal High-Speed Design Process SPECCTRAQuest Demonstration Introduction to SPECCTRAQuest Power Integrity,NOW,Ideal High-Speed Design Flow,Model Development & Verification,Topology Entry & Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Model Development & Verification,Need Flexible Device Modeling Language (DML),Todays models come in many styles and formats Cadence DML can model all formats AND advanced behaviors (for example, Merced / Itanium),Quad Models,Package, Transmission Line, Connector, Cable Models,EBD Models,Cadence DML,cant do “M” element today,Ideal High-Speed Design Flow,Model Development & Verification,Topology Entry & Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Pre-Route Soln-Space Analysis,Pre-Route Solution Space Analysis,Exhaustive “pre-layout” analysis of manufacturing and design variances Used to define topologies, routing rules and termination strategies Crosstalk and data pattern dependencies may be taken into consideration Swept-parameter analysis is used extensively to cover all combinations of conditions Need flexibility to define any kind of simulation and any kind of measurement criteria,Output of pre-layout process is an electronic constraint file that can be used to guide the layout process,Analyze,Topology Templates,Derive and Save “Solution Space”,Constrain,Ideal High-Speed Design Flow,Model Development & Verification,Topology Entry & Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Topology Entry & Floorplanning,High-Speed PCB Design Now Requires Both Electronic Inputs to Floorplanning & Routing,Topology Entry and Floorplanning,Design rules derived from solution space analysis guide the placement process Constraint Manager spreadsheets plays a key role in guiding / evaluating component placement Margin columns show difference between constraint and design value Fast feedback Color-coded status,Topology Templates,Ideal High-Speed Design Flow,Model Development & Verification,Topology Entry & Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Constraint Driven Layout,ConceptHDL Capture,SPECCTRAQuest Exploration,SPECCTRAQuest Floorplanning,Allegro/APD Layout,Constraint Manager,Capture,Exploration,Floorplanning,Layout,GUI,GUI,GUI,GUI,Constraints,Constraints,Constraints,Constraints,?,?,?,ePlanner/QUAD,SPICE,HyperLynx,ViewDraw,ICX,Design,Board Station,PADS,VeriBest,Architect,ePlanner,Constraint Management Today,PSD 14.0 Constraint Manager,Common, powerful environment for constraint entry / editing / management and verification Single mechanism for managing constraints throughout the design process,Constraint Manager Key Features,Spreadsheet-based graphical interface No cryptic formats or cumbersome updating Provides unsurpassed Integration across the entire design flow Consistent Front to Back solution No messy translations with static constraint data Directly integrated with schematic and PCB databases Analysis engines can update spreadsheet data interactively,Constraint Manager Hierarchy,Allows constraints to be managed hierarchically Groups of rules are maintained as Electrical Constraint Sets (ECSets) Provides single point for updating rules or assigning to nets ECSets can be applied to groups of nets (buses) with individual overrides,Constraint Manager Systems,Support for system level constraints Constraints can span PCB boundaries,Topology Templates,Constraint Driven Layout,Guides: Floorplanning Hand Layout Auto-Route,Constraint Driven Layout,Design rule violations during interactive routing are identified in real-time Autorouter follows design rules - powerful integration with SPECCTRA! Because solution space analysis has defined a set of conditions under which the nets are known to work, chance of first-pass success is high. Nets can be ripped up and rerouted, as long as they still adhere to the design rules,Ideal High-Speed Design Flow,Model Development & Verification,Topology Entry & Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,Post Route Analysis Verification,Verification,Agenda,What is High-Speed Design? Ideal High-Speed Design Process Introduction to SPECCTRAQuest Power Integrity SPECCTRAQuest Demonstration,NOW,SPECCTRAQuest Power Integrity Module,The Future of Power Delivery System Design,SPECCTRAQuest Power Integrity,Innovative technology developed and proven by Sun Microsystems, now commercialized by Cadence Design Systems, Inc. to address Power Delivery issues in high-speed PCB System Designs. A design tool / methodology used to design and optimize the frequency-dependent characteristics of Power Delivery Systems in high-speed system designs An integrated solution to allow many quick iterations of “change-simulate-analyze”,Power Delivery Requirements Trend,Power dissipation and longer battery life fueling decreasing chip power supply voltages Maximum allowable supply ripple decreases accordingly SoC, SiP fueling trend towards devices with large number of devices The instantaneous switching current required is enormous The maximum acceptable power supply ripple voltage determines the target impedance which must be maintained across the PCB Maximum supply impedance must be less than 0.002 Ohms,Power Delivery System Design Challenges,Power supply droop Alters system timing and can cause Setup failures Can cause sampling errors that results in a system crash Unreliable power delivery system design can cause increased common-mode EMI preventing product shipment due to compliance problems Power delivery system impedance is frequency-dependent Must be controlled for all frequency range of all transient currents,Increases Development Costs and Time to Market is LOST!,Power Delivery System Design - How it is done today,Standalone analysis tools Design data translation is left up to the user Changes to the design resulting from simulation is manual Use Time Domain simulation Power delivery system impedance is frequency-dependent! With only time domain simulation, it is like searching for needle in a haystack Over design - add more de-coupling capacitors than necessary Expensive solution that may not work,The Cadence approach,Allow users to determine the needs of the power delivery system Target impedance Decoupling capacitor requirements Provide frequency domain analysis to find problem areas Provide an integrated PCB design editor to optimize capacitor placement,Develop reliable power delivery system while shortening design cycle time,SPECCTRAQuest Power Integrity - Software Components,Frequency-domain analysis engine Integrated PCB editor that includes Decoupling capacitor placement environment Impedance requirements calculator Decoupling requirements wizard High speed capacitor library / library editor,Isolating Decoupling Problem Areas,Device Placement Decoupling Capacitors,Capacitors can be selected from the decoupling “menu” and placed into the design The effective decoupling radius is automatically displayed as the capacitor is positioned Designers continue to adjust capacitor selection & placement until performance of the PDS is acceptable,Allows many “change-simulate-analyze” cycles in a short time,Release,Available with PSD release version 14.1 Scheduled for late Q2, 2001 First release available on Sun Solaris (7 / 8) only Other platforms to follow with next major release,SPECCTRAQuest Power Integrity - Summary,Innovative technology developed and proven by Sun Microsystems, commercialized by Cadence Combined toolset and methodology for the design and analysis of high performance power delivery systems Offered as an option to SPECCTRAQuest, integrated with Allegro Part of Cadences complete family of Signal Integrity / Power Delivery / EMI solutions,Shortens Development Cycle and Time to Market!,Agenda,What is High-Speed Design? Ideal High-Speed Design Process Introduction to SPECCTRAQuest Power Integrity SPECCTRAQuest Demonstration,NOW,SPECCTRAQuest Demonstration,(please ask questions as we proceed!),What You Will See,Intel PIII / BX Reference Design 100 MHz Front-Side Bus Analysis & Constraint Process Board Level Electrical Level Constraint Integration Advanced Processing,Post-Route DRC Verification,DRC checks identify areas which do not comply with design rules Net is marked visually Identifies which constraint was violated DRC provides a “first pass” check faster than simulation Design rules can also be applied without ripping up etch, to pinpoint problems in boards routed before design rules were available,Post-Route Analysis Verification,Post-layout simulation now becomes a “verification” process Chances of first-time success are high if a thorough solution-space analysis was performed Nets can be extracted individually and analyzed in-depth if problems are found SQ has the only optimized spice analysis engine that is integrated with PCB layout and field solvers,SPECCTRAQuest: Integrated Constraint & Analysis,Model Development & Verification,Topology Entry & Floorplanning,Constraint Driven Layout,Analyze,Constrain,Development Process Flow,Pre-Route Soln-Space Analysis,