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第8章有限状态机的设计,VerilogHDL数字系统设计及仿真,2,本章内容,有限状态机的类型一段式、两段式和三段式状态机写法状态编码,3,有限状态机的类型,moore型，也称为摩尔型mealy型，也称为米利型,4,moore型红绿灯,状态转换图,5,模型代码,moduletrafficlight1(clock,reset,red,yellow,green);inputclock,reset;/输入时钟和复位信号outputred,yellow,green;/输出红黄绿的驱动信号regred,yellow,green;reg1:0current_state,next_state;/保存当前状态和下一状态parameterred_state=2b00,yellow_state=2b01,green_state=2b10,delay_r2y=4d8,delay_y2g=4d3,delay_g2r=4d11;/参数声明,6,/第一段always，用于把下一状态赋值给当前状态always(posedgeclockorposedgereset)beginif(reset)current_state=red_state;elsecurrent_state=next_state;end,7,/第二段always，用于根据当前状态判断下一状态，并产生输出always(current_state)begincase(current_state)red_state:beginred=1;yellow=0;green=0;repeat(delay_r2y)(posedgeclock);next_state=yellow_state;end,8,完成状态描述,yellow_state:beginred=0;yellow=1;green=0;repeat(delay_y2g)(posedgeclock);next_state=green_state;endgreen_state:beginred=0;yellow=0;green=1;repeat(delay_g2r)(posedgeclock);next_state=red_state;enddefault:beginred=1;yellow=0;green=0;next_state=red_state;endendcaseendendmodule,9,测试信号,initialclock=0;always#10clock=clock;initialbeginreset=1;#1reset=0;/产生一个复位信号沿#10000reset=1;/主要工作时间#20$stop;end,10,功能仿真时序仿真,11,增加一个可变计数器,always(posedgeclockorposedgereset)beginif(reset)light_count=0;elseif(light_count=light_delay)/达到规定的计数值light_delay时置1light_count=1;elselight_count=light_count+1;end,12,case(current_state)red_state:beginred=1;yellow=0;green=0;light_delay=red_delay;if(light_count=light_delay)next_state=yellow_state;endyellow_state:beginred=0;yellow=1;green=0;light_delay=yellow_delay;if(light_count=light_delay)next_state=green_state;end,13,green_state:beginred=0;yellow=0;green=1;light_delay=green_delay;/延迟时间被赋值为green时的延迟if(light_count=light_delay)/达到延迟时间变为下一状态next_state=red_state;end,14,mealy型红绿灯,状态转换图,15,设计模块,moduletrafficlight3(clock,reset,x,red,yellow,green);inputclock,reset;inputx;/多添加了一个输入端xoutputred,yellow,green;regred,yellow,green;reg1:0current_state,next_state;parameterred_state=2b00,yellow_state=2b01,green_state=2b10,delay_r2y=4d8,delay_y2g=4d3,delay_g2r=4d11;,16,always(posedgeclockorposedgereset)/原态和新态的转换beginif(reset)current_state=red_state;elsecurrent_state=next_state;end,17,always(current_stateorx)begincase(current_state)red_state:beginred=1;yellow=0;green=0;if(x=1)/红灯时若x为1，则把下一状态指向黄灯beginrepeat(delay_r2y)(posedgeclock);next_state=yellow_state;endend,18,yellow_state:beginred=0;yellow=1;green=0;repeat(delay_y2g)(posedgeclock);next_state=green_state;endgreen_state:beginred=0;yellow=0;green=1;repeat(delay_g2r)(posedgeclock);next_state=red_state;end,19,default:beginred=1;yellow=0;green=0;next_state=red_state;endendcaseendendmodule,20,仿真波形,21,一段式状态机,检测输入信号0110状态转换图,22,状态转换表,23,声明部分,modulefsm_seq1(x,z,clk,reset);inputx,clk,reset;outputz;regz;reg2:0state;parameters0=d0,s1=d1,s2=d2,s3=d3,s4=d4;,24,一段always,always(posedgeclkorposedgereset)/仅有一段alwaysbeginif(reset)/复位信号有效beginstate=s0;/回到初始状态z=0;/z输出0end,25,S0状态,S1状态,elsecasex(state)s0:beginif(x=1)beginstate=s0;z=0;endelsebeginstate=s1;z=0;endend,s1:beginif(x=0)beginstate=s1;z=0;endelsebeginstate=s2;z=0;endend,26,S2状态,S3状态,s2:beginif(x=0)beginstate=s1;z=0;endelsebeginstate=s3;z=0;endend,s3:beginif(x=0)beginstate=s4;z=1;endelsebeginstate=s0;z=0;endend,27,S4状态,结束,s4:beginif(x=0)beginstate=s1;z=0;endelsebeginstate=s2;z=0;endend,default:state=s0;endcaseendendmodule,28,功能仿真波形时序仿真波形,29,一段式特点,仅有一段always结构，里面包含了状态转换、复位和输出；always结构的敏感列表是时钟沿，所以最后的输出结构是以寄存器形式输出，即时序逻辑输出的,30,两段式状态机,声明部分,modulefsm_seq2(x,z,clk,reset);inputx,clk,reset;outputz;regz;reg2:0state,nstate;/state表示原态，nstate表示新态parameters0=d0,s1=d1,s2=d2,s3=d3,s4=d4;,31,第一段always,第二段always,always(posedgeclkorposedgereset)beginif(reset)state=s0;elsestate=nstate;end,always(stateorx)begincasex(state)s0:beginif(x=1)beginnstate=s0;z=0;endelsebeginnstate=s1;z=0;endend,32,s1,s2,s1:beginif(x=0)beginnstate=s1;z=0;endelsebeginnstate=s2;z=0;endend,s2:beginif(x=0)beginnstate=s1;z=0;endelsebeginnstate=s3;z=0;endend,33,s3,s4,s3:beginif(x=0)beginnstate=s4;z=1;endelsebeginnstate=s0;z=0;endend,s4:beginif(x=0)beginnstate=s1;z=0;endelsebeginnstate=s2;z=0;endenddefault:nstate=s0;endcaseend,34,仿真波形,fsm_seq1的输出z发生在每个clk上升沿的位置，fsm_seq2的输出z发生在x变化的位置fsm_seq1的输出维持一个周期，fsm_seq2的输出维持半个周期。最后的输出采用组合逻辑电路,35,三段式状态机,除always外无区别,/第一段always，完成原态到新态的转换always(posedgeclkorposedgereset)beginif(reset)state=s0;elsestate=nstate;end,36,/第二段always，指定新态的变化always(stateorx)begincasex(state)s0:beginif(x=1)nstate=s0;elsenstate=s1;ends1:beginif(x=0)nstate=s1;elsenstate=s2;end,s2:beginif(x=0)nstate=s1;elsenstate=s3;ends3:beginif(x=0)nstate=s4;elsenstate=s0;ends4:beginif(x=0)nstate=s1;elsenstate=s2;enddefault:nstate=s0;endcaseend,37,always(stateorx)/第三段always，指定不同状态下的输出begincasex(state)s0:z=0;s1:z=0;s2:z=0;s3:beginif(x=0)z=1;elsez=0;ends4:z=0;default:z=0;endcaseend,38,Mealy型的五种输出敏感列表,always(stateorx)if(state=xxxandx=yyy)always(state)always(nstate)always(posedgeclk)case(state)always(posedgeclk)case(nstate),39,时序图,40,Moore型的四种输出敏感列表,always(state)always(nstate)always(posedgeclk)case(state)always(posedgeclk)case(nstate),41,时序图,42,状态编码的选择,二进制码parameters0=3b000,s1=3b001,s2=3b010,s3=3b011,s4=3b100;格雷码parameters0=3b000,s1=3b001,s2=3b011,s3=3b010,s4=3b110;独热码parameters0=5b00001,s1=5b00010,s2=5b00100,s3=5b01000,s4=5b10000;,43,独热码状态机,状态转换图,44,设计代码,声明部分,moduleex8_1(clock,reset,x,y1,y2);inputclock,reset;inputx;outputy1,y2;regy1,y2;reg3:0cstate,nstate;/本例中采用独热码，当然使用二进制码也可parameters0=4b0001,s1=4b0010,s2=4b0100,s3=4b1000;,45,/第一段always，原态变新态always(posedgeclockorposedgereset)beginif(reset)cstate=s0;elsecstate=nstate;end,46,/第二段always，状态转换always(cstateorx)begincase(cstate)s0:beginif(x=0)nstate=s1;elsenstate=s3;ends1:beginif(x=0)nstate=s2;elsenstate=s0;end,s2:beginif(x=0)nstate=s3;elsenstate=s1;ends3:beginif(x=0)nstate=s0;elsenstate=s2;enddefault:nstate=s0;endcaseend,47,s2:beginif(x=0)y1=0;elsey1=0;ends3:beginif(x=0)y1=0;elsey1=1;enddefault:y1=0;endcaseend,/第三段always，产生输出always(cstateorx)begincase(cstate)s0:beginif(x=0)y1=1;elsey1=0;ends1:beginif(x=0)y1=0;elsey1=0;end,懒！,48,简化输出,always(cstateorx)/在输出比较简单时，也可以使用if来确定输出值beginif(cstate=s0end,49,进一步精简,always(cstateorx)beginif(cstate=s0end,50,功能仿真波形时序仿真波形,51,格雷码状态机,状态转换图,52,声明部分,moduleex8_2(clock,reset,a,z1,z2,z3,z4);inputclock,reset;inputa;outputz1,z2,z3,z4;regz1,z2,z3,z4;reg1:0cs,ns;parameters0=2b00,s1=2b01,s2=2b11,s3=2b10;/格雷码,53,always(posedgeclockorposedgereset)beginif(reset)cs=s0;elsecs=ns;end,54,always(csora)begincase(cs)s0:beginif(a=0)ns=s0;elsens=s1;ends1:beginif(a=0)ns=s0;elsens=s2;end,s2:beginif(a=0)ns=s0;elsens=s3;ends3:beginif(a=0)ns=s0;elsens=s3;enddefault:ns=s0;endcaseend,55,/第二个输出，使用时钟沿和下一状态做敏感列表always(posedgeclock)beginif(ns=s3end,/第一个输出，使用时钟沿和当前状态做敏感列表always(posedgeclock)beginif(cs=s3end,56,/第三个输出，使用当前状态做敏感列表always(cs)beginif(cs=s3end,/第四个输出，使用下一状态做敏感列表always(ns)beginif(ns=s3end,57,仿真波形图,
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