无线局域网接收器的高效自动增益控制算法和结构毕业论文翻译

无线局域网接收器的高效自动增益控制算法和结构Il-Gu Lee *, Sok-Kyu Lee下一代无线局域网研究团队，电子和电信研究院，柯亭161栋，顾儒城区，大田305700，大韩民国2006年2月23日收稿；2006年10月31日收到修订的稿件；2006年11月1日收录2007年1月11日可在线使用摘要接收机的性能前端限制了所给定的通信链路的质量和范围。基于明确定义的系统参数和结构的设计可以使整个系统在性能、成本和市场化方面有巨大的差异。值得强调的是，我们需要一种改进的数字自动增益控制(AGC)，应用于多输入多输出、正交频分复用(mimo - ofdm)的无线局域网(WLANs),争取成为即将到来的802.11n标准（在2004年8月，Heejung Yu et al.建议采用无线ETRI局域网作为泰科全球网络、IEEE 802.11文件（文件号11-04-0923-00-000n）的说明; H.Yu,T.Jeon,S.Lee,为下一代无线局域网设计的双频MIMO-OFDM系统在2005年5月电机及电子学工程师联合会通信国际会议（ICC）上获得通过）。在本文中，我们提出一种有效的算法和实施面向下一代无线局域网的数字自动增益控制系统。该自动增益控制算法有两个反馈增益控制以提高收敛速度,且同时保持AGC电路的稳定性。另外，在各种满足不动点约束和精度要求的实验中获得了实际应用中需要的一套完整参数。关键词：自动增益控制，无线局域网; MIMO-OFDM技术，接收器结构1、简介AGC电路应用于许多系统，这些系统的输入信号电平在非常大的动态范围内变化。在高数据传输速率的数字通信系统中，尤其是在突发包分组交换系统中，如无线局域网，每个数据包开始会引入了一个大信号变化。来解调一个改善信噪比的接收信号，自动增益控制可用于维持基带信号的平均功率在我们期望值的附近。 AGC对于应用于下一代无线局域网技术的MIMO-OFDM具有重要意义，它确保实现接收端的性噪比满足实际要求，从而确保实数据传输速率。过去已经有一些关于自动增益控制的研究，这些研究提出自动增益控制算法和目前实施所遇到的问题。在文献3,4中，作者提出了一种实现简单的数字自动增益控制结构，其定位于IEEE802.11a标准。文献3的作者提出一种简单的多站式自动增益控制方案。在文献4中，作者提出了一种基于双自相关的同步自动增益控制接口的方案。在这些论文中，对理论问题进行了分析，并且提供了没有详细考虑实施过程中的限制条件而得到的仿真结果。在本文中，提出了新的AGC结构，它包括一个大增益更新循环和一个小增益更新循环，用来提高收敛速度，并同时保持AGC电路的稳定。此外，它还可以动态控制MIMO- OFDM系统接收到大变化能量信号的增益，该信号能量变化由随时间频率偏移的多径衰落引起的。本文的其余部分安排如下：在第二节中，给出下一代无线局域网的框架模型；在第三节中，描述了接收器的整体结构。后面详细地描述每个子块，并给出各自部分结构：自动增益控制在第4节；数字放大器在第5节载以及波监听在第6节；在第7节中，展现该设计的性能；最后，在第8节我们得出结论。2、框架模型下一代WLAN是一种基于分组的高通量MIMO - OFDM系统，该系统工作在 5 GHz频带。图1和2显示了下一代无线局域网的数据包结构 ，该结构在文献1,2中有详细描述。每个数据包包含一个检测头， 预测信道和同步信道。报头可以被双方识别以用来通信链接。传统的OFDM报头由10个相同的短正交频分复用(OFDM)辅助符号（ti，i = 1，210；每个符号包含16个样品）和2个相同的长正交频分复用(OFDM) 辅助符号（Ti，i = 1，2；每个符号包含64个像IEEE802.11a的样品）。在MIMO- OFDM模式，长正交频分复用(OFDM)符号，（Ti，i = 1，2），该符号在信号之后传输，提供信道测量能力。短的辅助符号是用于信号检测，自动增益控制，多样性，粗采样和频率同步。为了确保接收到的信号增益控制及时和提供稳定增益的可靠传输，接收器设计人员可以使用短报头来调整接收到的信号强度达到到最佳水平，该调整通过在接收信号路径上可动态调节的各种信号处理元件来实现。图1 传统的OFDM数据包结构模型图2 MIMO-OFDM数据包结构模型长辅助符号被设计用来信道预测和精细频移校正。该信号包括奇偶校验，长度和速率等。有一个短的保护区间（GI）和一个长的保护区间（GI2）组成32或64个数据样本，分别用来作为传统OFDM的长辅助符号和长MIMO - OFDM的辅助符号。在OFDM数据域中，每个波段有四个子载波作为试点被插入到的位置-21，-7，7，和21。，子载波总数分别为52和104。3、接收器结构接收器的整体框图如图3所示。从三个天线接收到的3个信号 输入数字放大器用来调整即将到来信号的能力达到目标值。数字前端操作只适用于来自3个可用路径出来的两个接收信号，达到降低实施复杂度的目的。输入信号能量测量和增益更新是在AGC模块中计算的。数字放大器的输出被监测用来检测信号是否太大或者太小大而超出载波的敏感范围。接收到的信号被引向到一个+10和-10M赫兹频率变化的频道混合器。OFDM输入符号缓冲到FFT输入缓冲区，并且在输入FFT前对载波频率偏移（CFO）进行纠正。利用相导频跟踪块对频率和相位的误差进行估计和纠正。通过短报头和长报头的自相关的结果来实现CFO估计，帧同步和带检测。同步程序完成后，CFO补偿数据包由128点、基-23 DIF FFT块转化为频域。该FFT输出是位反转顺序，该序列通过使用迫零（ZF）方法输入到MIMO检测中2。ListenJishu do de xnho bi dngxing do yg tngdo hnh q wi 10 h 10 zho h de pnl fshng binhu. OFDM fho de shr hunchng FFT shr do hunchng q, zib pnl pin y (shux ciw gun) sh zi FFT shr jizhng. De pnl h xingwi wch gj, bng lyng zi xing do pn gnzng kui de jizhng. Shux ciw gun gj, zhng tngb h di jinc sh yu yg dunq h chngq de xyn z xinggun de jigu. Tngb hu chngx wnchng hu, shux ciw gun bchngDictionary - View detailed dictionary图3 带3天线的双频段MIMO-OFDM接收机前端结构4、自动增益控制接收信号幅度的自动调整使得ADC的动态范围得以充分利用。AGC实际工作的状态转移图如图4所示。当AGC自动增益控制块的启动信号（agc_en）为低电平时，该自动增益控制块的状态从任意状态变成空闲状态。第一个状态是功率测量状态（MSR），它判定在放大器增益调整之前信号峰值是否在ADC的动态范围之内。如图5所示，信号功率的衡量是根据每个天线积累的实部绝对值（同相分量）和虚部（正交分量）的能量来测量信号的信号功率。用0.8最小二乘方法（32个在40 MHz采样的样本）来测量输入信号的功率。所选择的转换为，通过采用信号能量的对数值可以减少信号能量值的范围。如果在信号功率测量期间，测量得到的信号能力不在ADC（ADC饱和度）的动态范围内，能量测量将停止，同时AGC启用大的增益更新状态（Update_L），用大的增益控制值来粗调增益以加快增益调整。通过寄存器的设定值（agc_gainl）来迅速降低放大器的增益，以达到加速收敛的目的。增益调整的尺度固定为3分贝。在信号功率测量期间，增益更新是由于在ADC饱和度观察时候ADC已经饱和如果在信号功率测量期间，ADC没有饱和度，则测量的能量和参考能量进行比较，计算出一个误差信号。误差信号幅度和参考值的比较是在一个小增益更新状态（Update_S）中进行的。通过测量能量的对数值和目标能量值的比较，可以选择一个最大的信噪比，和最小的饱和效应的信号。如果测得的能量（agc_pwr_log）比目标能量（agc_vref）小，由于这是一个可编程的寄存器，我们可以调整增益，在增益改变信号固定下来之后，通过寄存器的值使信号能量等于目标能量 如果测得的能量（agc_pwr_log）比目标能量（agc_vref）大，则增益减小，甚至设置agc_gains，这是寄存器编程。这种额外的增益抑制在接收到的信号是很大时可以加快增益调整和防止饱和情况发生。一旦放大器的增益更新，自动增益控制模块在等待状态内等待寄存器编程一段时间（agc_delay）。该寄存器的值应足够大，使得信号能很好的在增益变化可控范围之内。Wait_cont和Wait_last状态分别是持续增益控制进程和最后增益控制的等待状态。在等待状态结束后，信号的能量测量和增益的更新如此反复进行，直到测量的功能量比目标能量小，此时增益进行相应的更新。最初的增益由可编程寄存器（agc_ginit）来设定。图4 AGC状态转移图图5 AGC方框图5、数字放大器数字放大器是通过放大或衰减来调整信号能量的大小，它根据现有的增益状态调整可编程寄存器使得信号能量达到目标能量。数字放大器包括一个增益状态单元，它可以存储对接收的数据包处理所选定的增益状态该增益状态单元从最高增益状态开始，以确保最低的功率信号可以被检测和处理。两个接收信号的路径上都应用到了相同的增益调整量。利用像图6所示的粗增益步骤，简化了数字放大器的实施。更新的增益量划分为6分贝和3分贝两个步骤， 6分贝增益更新步骤首先应用到输入信号，然后再用3分贝步骤进行增益调整。当增益控制值和AGC参考值相同时，将不存在增益调整。图6 数字放大器的方框图6、监控ADC饱和的载波监听不管ADC是否饱和，输入信号的存在都可以通过监测被检测到。为了提高ADC饱和度检测的可靠性，使用16个在40 MHz采样的连续样品。考虑一个从天线0接收到的信号的实部部分。如果ADC输出样本的数值绝对值大于某个阈值（cs_th_sat，500），且大于或等于一个可编程的寄存器数值（cs_th_cnt_sat，4），我们就标记ADC已经达到饱和。 4个信号的组成部分（两个天线接收到信号的实部和虚部）中任意一个都可以标记ADC已经达到饱和。载波监听的框图如图7所示。图7 载波监听的方框图7、性能评估我们运用了50 ns的均方根时延扩展信道模型。同时，该模型包括射频损伤和一个具有10 dB补偿的拉普功率放大器和一个具有零极点相位噪声的模型。发射机和接收机振荡器的频率不稳定会引起残留频率误差的存在。由于模数转换器（ADC）的使用，使得所有仿真事件都有时间/频率偏移。数据包大小固定为1 K字节。仿真模型的传输速率固定为36 Mbps（兆比特每秒）和54 Mbps（兆比特每秒），使用QPSK，16 -QAM和64- QAM的调制方案，这些方案都采用MIMO双波段技术。因此，实际的数据传输速率分别为72 Mbps（兆比特每秒）的，144 Mbps（兆比特每秒）和216 Mbps（兆比特每秒）。使用不同的调制方案仿真得到的包差错率绘制在图8上。FL和FX分别指仿真结果中的浮点类型和定点类型。虽然大多数调制方案的定点与浮点有相似的性能，然而在使用16 -QAM和64- QAM的调制方案时，由量化误差引起的性能上的差距很明显，在10的包差错率时，两种方案损失的信噪比分别为0.3和0.7分贝。我们在图8表明：推荐的算法及其实施在多径衰落的50ns均方根时延扩展和40 ppm的时间/频率偏移中具有很好的效果。就已知的约束而言，该算法在28分贝信噪比大约有10包差错率。考虑到实施的复杂性和性能之间的折中，我们提出的算法和它的实施对于MIMO- OFDM系统接收器而言，是一个很好的折中解决方案。图8 调制方案在包差错率之间的比较在图9中，在16-QAM和R= 3/ 4条件下，目标信号在仿真过程中的幅度调整变化。agc_vref是在3分贝条件下，在AGC完成之后的目标信号幅度。例如，agc_vref= 13对应着目标信号的幅度为2 （13/2）。我们发现，通过对信号频带的使用和双频段的使用进行不同的设置，接收机的性能可以得到提高，如表1所示。如表2所示，agc_gainl和agc_gains寄存器值的设置需要考虑包差错率的结果，和输入信号的能量范围和更新的次数，因为AGC需要在短报头结束之前很好的完成。agc_init是初始增益设置。如果信号需要被放大，初始增益将增加到最大值。如果信号很大，需要加以抑制，初始增益将减少到0。当agc_ginit是20，增益控制为3分贝时，最大的信号抑制可达到20*3 = 60分贝，最大的信号放大可以达到（32-20）*3 = 36分贝。初始增益应该设置得足够大以达到具有抑制信号的能力。在agc_ginit= 20这个例子中，有60分贝的空间去抑制信号。自动增益控制寄存器仿真参数的设置如表1所示。图9 AGC参考值 (agc_vref)的调整表1 可编程寄存器的设置AGC registersValues agc_delay32agc_gainl12agc_gains8agc_ginit20agc_vref13 (双频带使用)/10 (单频带使用)表2 AGC循环次数agc_gainlagc_gains# of update_L# of update_SPER (%)012020918.410172816.111464813.364460812.7128858912.71812472124.6接收器中AGC的快速收敛电路减少了将接收信号调整到ADC工作范围内的时间。本文提出的的数字AGC电路包括一个大增益更新循环和一个小增益更新循环，用来加快收敛速度，并且同时维持控制输入信号电平稳定。图10为1000包，在27分贝、64 - QAM和R= 3 /4 条件下的仿真结果。大增益更新循环可以很快的将接收信号调整到期望的范围。小增益更新循环慢慢抚平接收信号，以避免AD转换器达到饱和并且加输入信号电平的收敛快速度。数字放大器输入信号电平与时间关系数字放大器输出信号电平与时间关系图10 数字放大器输入/输出信号电平8、结论在本论文中，设计的自动增益控制电路用来调整接收信号的强度，通过接收路径上可以处理各种信号的大动态范围元件来使接收信号达到一个恒定的最佳能量水平附近。该自动增益控制电路包括一个大增益更新循环和一个小增益更新循环，用来加快收敛速度，并且同时保持自动增益控制电路的稳定。此外，它可以用来动态控制由多径衰落、时间和频率偏移引起大变化范围接收信号的增益， 以确保及时地对接收信号进行增益控制，提供稳定增益进而得到可靠的传输。参考文献1 Heejung Yu et al., IEEE 802.11 wireless LANs ETRI proposal specication for IEEE 802.11 TGn, IEEE 802.11 document, doc. No. 1104092300000n, August, 2004.2 H. Yu, T. Jeon, S. Lee, Design of dualband MIMO-OFDM system for next generation wireless LAN, in: IEEE International Conference on Communications (ICC), May, 2005.3 V.P.G. Jimenez, M.J.F.G. Garcia, F.J.G. Serrano, A.G. Armada, Design and implementation of synchronization and AGC for OFDMbased WLAN receivers, IEEE Trans. Consum. Electron. 50 (4) (2004) 10161025.4 A. Fort, W. Eberle, Synchronization and AGC proposal forIEEE 802.11a burst OFDM systems, GLOBECOM 3 (12) (2003) 13351338.Ecient automatic gain control algorithm and architecture for wireless LAN receiversIlGu Lee *, SokKyu LeeNext Generation Wireless LAN Research Team, ETRI, 161 Gajeongdong, Yuseonggu, Daejeon 305700, Republic of KoreaReceived 23 February 2006; received in revised form 31 October 2006; accepted 1 November 2006Available online 11 January 2007AbstractThe performance of a receiver frontend limits the quality and range of the given communication link. An appropriate design based on welldened system parameters and architecture can make a huge dierence in the performance, cost and marketability of the entire system. In particular, there is a need for improved digital automatic gain control (AGC) for use in multiinput multioutput orthogonal frequency division multiplexing (MIMOOFDM) systems with application to wireless local area networks (WLANs), targeted for the upcoming 802.11n standard Heejung Yu et al., IEEE 802.11 wireless LANs ETRI proposal specication for IEEE 802.11 TGn, IEEE 802.11 document, doc. No. 1104092300000n, August, 2004; H. Yu, T. Jeon, S. Lee, Design of dualband MIMOOFDM system for next generation wireless LAN, in: IEEE International Conference on Communications (ICC), May, 2005. In this paper, we propose an ecient algorithm and implementation of the digital AGC for next generation WLANs. The proposed AGC algorithm has two feedback loops for gain control to improve convergence speed, and at the same time maintains the stability of the AGC circuit. Also, a complete set of parameters for practical implementation is obtained by various experiments with xed point constraints and accuracy requirements.Keywords: AGC; WLAN; MIMOOFDM; Receiver architecture1. IntroductionAGC circuits are employed in many systems where the level of an incoming signal can vary over a wide dynamic range. In high data rate digital communication systems, and especially in burst packet switched systems such as WLANs, the start of each packet introduces a large signal variation. To demodulate a received signal with an improved signaltonoise ratio, AGC can be used to hold the average power of the baseband signal close to a desired level. AGC implementation of highthroughput MIMOOFDM applications to nextgeneration WLANs is important to ensuring achievable operating SNR at the receiver and, consequently, achievable data rates.There have been several research contributions that provide automatic gain control algorithms and present implementation issues. In 3,4, the authors present the implementation of a simple digital automatic gain control architecture targeting the IEEE 802.11a standard. The authors of 3 propose a simple multistop AGC scheme. In 4,an AGC interface with a synchronization scheme based on double autocorrelation is proposed. In those papers, the theoretical problem is analyzed and simulation results are provided without considering implementation constraints in detail.In this paper, the proposed architecture includes a large gain update loop and a small gain update loop to improve convergence speed and at the same time maintain the stability of the AGC circuit. Moreover, it can be used to dynamically control the gain of the received signal for MIMOOFDM systems with large variations in received signal power caused by multipath fading with time and frequency oset.The remainder of this paper is organized as follows. In Section 2, the frame model is given for next generation wireless LANs, and the overall receiver architecture is presented in Section 3. A detailed description for each subblock is then provided in their respective sections: automatic gain control in Section 4; carrier sensing block in Section 5; and digital amplier in Section 6. In Section 7, the performance of the proposed design is shown. Finally, we conclude in Section 8.2. Frame modelThe next generation WLAN is a packetbased highthroughput MIMOOFDM system in the 5 GHz band. Figs. 1 and 2 show the packet structure of next generation WLAN as specied by 1,2. Each packet contains a header for detection, channel estimation and synchronization. This preamble is known at both sides of the communication link. The legacy OFDM packet preamble consists of 10 identical short OFDM training symbols ti, i =1,2, .,10, each of which contains 16 samples; and two identical long OFDM symbols Ti, i =1,2, each of which contains 64 samples as in the IEEE 802.11a. For MIMOOFDM mode, two long OFDM symbols Ti, i = 3,4, are transmitted after the signal eld for providing channel measurement capability. The short training symbols are intended for signal detection, automatic gain control, diversity, coarse acquisition, and frequency synchronization purposes. In order to ensure timely gain control for the received signal and provide reliable transmission with stable gain, a receiver designer can use the short preamble to adjust the strength of the received signal to an optimum level within the dynamic range of various signal processing components in the received signal path.Fig. 1. The packet structure of the Legacy OFDM mode.Fig. 2. The packet structure of the MIMO-OFDM mode.The long training symbols are designed to be used for channel estimation and ne frequency oset correction. The signal eld includes information for parity, length and rate, etc. There is a short guard interval (GI) and a long guard interval (GI2) that consist of 32 or 64 data samples for the long legacyOFDM training symbol and the long MIMOOFDM training symbol, respectively. In the OFDM data eld, four subcarriers are inserted as pilots into positions 21, 7, 7, and 21 for each band. The total number of subcarriers is 52 and 104 in single and dual band mode, respectively.3. Receiver architectureThe overall receiver block diagram is shown in Fig. 3. The three received signals from 3 antennas are fed into digital ampliers to adjust the power of the incoming signals to the target value. The digital front end operations are applied to only the two received signals out of the 3 available paths to reduce implementation complexity. The power of the input signal is measured and gain update is calculated in the AGC block. The digital amplier output is monitored to detect if the signal is large or not for the carrier sensing purpose. The DC oset andI/Q imbalance that come from RF components and ADC are compensated in each signal path. The received signals are directed to a channel mixer for +10 and 10 MHz frequency shifting. The input OFDM symbol is buered into the FFT input buffer, and the carrier frequency oset (CFO) is corrected at the input of the FFT. The frequency and phase errors are estimated and corrected by using the pilot tones in the phase tracking block. The CFO estimation, frame synchronization and band detection are performed by an autocorrelation result of short and long preambles. After the synchronization process is done, the CFO compensated packets are transformed to the frequency domain by a 128point radix23 DIF FFT block. The output of FFT is the data in the bitreversed order, which is fed into the MIMO detector 2, which uses the zeroforcing (ZF) method.Fig. 3. The front-end architecture of dual-band MIMO-OFDM receiver with 3 antennas.4. Automatic gain controlThe amplitude of the received signal is adjusted so that the dynamic range of the ADC can be fully utilized. The state transition diagram implemented physically for the AGC is shown in Fig. 4. The AGC block state is changed to the idle state from whatever state the AGC is in when the AGC block enable (agc_en) is deactivated. The rst state is a power measurement state (MSR), which determines whether the peak signal is within the dynamic range of ADC before adjusting the amplier gain. As shown in Fig. 5, the signal power is measured by accumulating the absolute real (inphase) and imaginary (quadraturephase) components of each antenna. The power of the input signal is measured for 0.8 ls (32 samples at 40 MHz sampling). Out of the two estimated signal powers, the larger one is selected for gain update. The chosen signal power is converted to a logscale value. It is possible to reduce the range of values by taking log scale for the signal power. If the measured power is out of the dynamic range of ADC (ADC saturation) during this power measurement period, the power measurement is stopped and AGC makes a coarse adjustment with the large gain update state (Update_L) to speed up gain adjustment with the large gain control value. The amplier gain is reduced right away by the amount of the register programmed value (agc_gainl)in order to speed up convergence. The gain step is xed to 3 dB. The gain update due to ADC saturation is conducted only when ADC saturation is observed during the signal power measurement period. If ADC is not saturated during the power measurement period, the measured power is compared to a reference power to calculate an error signal, and the magnitude of the error signal is compared to a reference value in a small gain update state (Update_S). By comparing the measured logscale power with the target power that can be selected tomaximize the signal to noise ratio and minimize saturation eects. If the measured power (agc_pwr_log)is smaller than the target power (agc_vref), which is a programmable register, then the gain is adjusted so that the signal power is equal to the target power given by the register value after the signal is settled down for the gain change. If the measured signal power is larger than the target power, then the gain is reduced even more given the agc_gains, which is register programmable. This additional gain suppression will speed up the gain adjustment and prevent saturation when the received signal is large. Once the amplier gain is updated, the AGC block waits for a register programmed time period (agc_delay) in wait state. This register value should be suciently large so that the signal is well settled down to the gain change. The Wait_cont and Wait_last state are the wait states of the continued gain control process and the last gain control, respectively. Afterthe waiting period, the signal power measurement and gain update is repeated until themeasured power is smaller than the target power and gain is updated accordingly. The initial gain is given by the programmable register (agc_ginit).Fig. 4. State digram of AGC block.Fig. 5. Block diagram of AGC.5. Digital amplierThe digital amplier is used to scale the incoming signal power either by amplifying or attenuating and adjusts it to the target power specied in a programmable register according to the current gain state. The digital amplier includes a gain state unit that stores the selected gain state for processing of a received packet. The gain state unit begins with the highest gain state to ensure the lowest power signals can be detected and processed. The same amount of gain adjustment is applied to the two received signal paths. The implementation of the digital amplier is simplied by utilizing this coarse gain step as shown in Fig. 6. The amount of gain update is divided into 6 dB and 3 dB steps. The 6 dB step gain update is rstly applied to the incoming signal and then the 3 dB step gain adjustment is conducted. When the gain control value is the same as the AGC referencevalue, there is no gain adjustment.Fig. 6. Block diagram of digital amplier.6. Carrier sense by monitoring ADC saturationThe existence of the incoming signal is detectedby monitoring whether the ADC is saturated ornot. To improve the reliability of detecting the ADC saturation, 16 consecutive samples at 40 MHz sampling are used. Consider one signal component that is a real component from antenna 0. If the number of ADC output sample whose absolute value is larger than a certain threshold (cs_th_sat, 500) is larger than or equal to a register programmable value (cs_th_cnt_sat, 4), then we ag that the ADC is saturated. Any one of the 4 signalcomponents (real and imaginary components from the two antennas) can ag the ADC saturation. A block diagram is shown in Fig.7.Fig. 7. Block diagram of carrier sensing.7. Performance evaluationWe apply a 50 ns RMS delay spread channel model. As well, RF impairments, a RAPP power amplier with 10 dB backo and phase noise with a polezero model, are included. There can be a residual frequency error caused by frequency instabilities in the oscillators at the transmitter andreceiver. All simulation cases have time/frequency oset, introduced by an analogtodigital converter (ADC). Packet size is xed to 1 K bytes. Simulation modes are xed to 36 Mbps and 54 Mbps, employing the QPSK, 16QAM and 64QAM modul