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IC Manufacturing and YieldOutlineMotivationProduction EfficiencynDetermined by actions both on and off the manufacturing floornDesign for manufacturability (DFM): intended to improve production efficiencyHighVolumeManufacturingProcess DesignCircuit DesignOFFONVariabilitynThe most significant challenge in IC productionnTypes of variability:uhuman erroruequipment failureumaterial non-uniformityusubstrate inhomogeneityulithography spotsDeformationsnVariability leads to = deformationsnTypes of deformations1) Geometric:u lateral (across wafer)uvertical (into substrate)uspot defectsucrystal defects (vacancies, interstitials)2) Electrical:ulocal (per die)uglobal (per wafer)OutlineStatistical Process ControlControl ChartsControl Chart for AttributesDefect Chart!)(xcexPxcControl Limits for C-ChartccUCL3ccLCL3Control Limits for C-ChartccUCL3ccLCL3cExample48. 12537c13. 53ccUCL17. 23ccLCLDefect Density Chartncu Control Limits for U-ChartnuuUCL/3nuuLCL/3uExample83. 1)5)(20(183mncmuu64. 3/3nuuUCL02. 0/3nuuLCLControl Charts for VariablesControl of Mean and Variancexniinxnnxxxx1211niixxns12)(11Control Limits for MeannxUCL/32xCenter nxLCL/32where the grand average is: mxxxxm21Control Limits for Variance24413ccssUCLsCenter where: and c4 is a constantmiisms1124413ccssLCLModified Control Limits for MeanxncsxUCL43ncsxLCL43ExamplesxxmncsxUCL14. 434mncsxLCL88. 334ExamplemccssUCL19. 013244013244ccssLCLOutlineBackgroundComparing DistributionsHypothesis TestingBApBAnnsyyt11)(0iy2) 1() 1(222BABBAApnnsnsnsResultsAnalysis of VarianceANOVA Example616866614321yyyy64ySums of SquaresktttTyynS12)(ktnitiDtyyS112)(ktnittiRtyyS112)(Degrees of Freedom1 kT1 NDkNRMean SquaresTTTSs/2DDDSs/2RRRSs/2ANOVA Table for Defect DensityConclusions Factorial Designs2-Level Factorials(-1,1,1)(1,1,1)(-1,-1,1)(-1,1,-1)(1,1,-1)(-1,-1,-1)(1,-1,-1)23 Factorial CVD ExperimentMain EffectsInteraction EffectsYates AlgorithmYates ProcedureYates Algorithm IllustrationFractional Factorial DesignsFractional Factorial ExampleOutlineDefinitionsFunctional YieldPoisson ModelnLet: C = # of chips on a wafer, M = # of defect types nCM = number of unique ways in which M defects can be distributed on C chipsnExample: If there are 3 chips and 3 defect types (such as metal open, metal short, and metal 1 to metal 2 short, for example), then there are:CM = 33 = 27possible ways in which these 3 defects can be distributed over 3 chipsUnique Fault CombinationsPoisson DerivationnIf one chip contains no defects, the number of ways to distribute M defects among the remaining chips is:(C - 1)MnThus, the probability that a chip will have no defects of any type is:nSubstituting M = CAcD0, yield is # of chips with zero defects, or:nFor N chips to have zero defects this becomes:C1MCM- -11C- -M=)exp(11lim00DACYcDCACc)exp()exp(00DNADAYcNcMurphys Yield Integral0)(0dDDfeYDAcProbability Density FunctionsPoisson Model)exp()(000DAdDDfeYcDAcUniform Density FunctioncADuniformADeYc02210Triangular Density Function20210 cADtriangularADeYcSeeds Model 00exp1)(DDDDfcADY0lexponentia11Negative Binomial Modelf(D)D/D0 = 3 = 2 = 1Negative Binomial (cont.)01DAYcgammaParametric YieldnEvaluated using “Monte Carlo” simulationu Let all parameters vary at random according to a known distribution (usually normal)uMeasure the distribution in performancenRecall: nOr: IDnsat = f (tox, VTn)2TnGSoxnDnsatVVLWCIInput DistributionsnAssume: mean () and standard deviation () are known for tox, VTnnCalculate IDnsat for each combination of (tox, VTn)toxVTnOutput DistributionnYield (best parts) = nYield (worst parts) = adxxf)(cdxxf)(f(x)xIDnsatc (bad devices)b(moderate devices)a(good devices)
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