SoC设计方法与实现第二章设计流程

,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,Click to edit Master title style,第二章,SoC,设计流程,1,Outlines,Hardware/software(HW/SW)co-design flow,Standard cell based design flow,Duality of Software and Hardware,The hardware and software in an embedded system work together to solve a problem,How to partition is usually dictated by speed and cost,Dedicated hardware is fast,inflexible and expensive,Reconfigurable hardware is fast,flexible and more expensive,Software is slower,more flexible and cheaper,HW/SW Pro and Con,Hardware solution:PRO,Can be factors of 10X,100X or greater speed increase,Requires less processor complexity,so overall system is simpler,Less software design time required,Unless hardware bug is fatal,workarounds might be doable in software,Hardware solution:CON,Large NRE charges,Potentially long development cycle,Little or no margin for error,Only 50%of ASIC ICs work the first time,IP Royalty charges,Hardware design tools can be very costly,HW/SW Pro and Con,Software solution:PRO,No additional impact on materials costs,power requirements,circuit complexity,Bugs are easily dealt with,even in the field!,Software design tools are relatively inexpensive,Not sensitive to sales volumes,Software solutions:CON,Relative performance versus hardware is generally far inferior,Additional algorithmic requirements forces more processing power,Bigger,faster,processors,More memory,Bigger power supply,RTOS may be necessary(royalties),More uncertainty in software development schedule,HW/SW Co-Design:New Design Methodology,ESL design make co-design easier,HW/SW partitioning,Co-specification,co-analysis,co-simulation,co-verification,Interface synthesis,Verification of complete system both HW/SW,ESL Co-design Flow,SoC Design Flow,Hardware/software co-design flow,Detailed hardware design flow,Standard Cell Based ASIC Design Flow,Traditional ASIC Design Flow cont.,Detailed Design Flow,Detailed Design Flow,cont.,Detailed Design Flow,cont.,Thank you,14,