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Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-1Chapter 7 MOSFETs in ICs Scaling,Leakage,and Other Topics 7.1 Technology Scaling -for Cost,Speed,and Power ConsumptionNew technology node every two years or so.Defined by minimum line width-spacing average.Feature sizes are 70%of previous nodes.Reduction of circuit area by 2 good for cost and speed.YEAR19921995199719992001200320052007Technology Generation0.5m mm0.35m mm0.25m mm0.18m mm0.13m mm90nm65nm45nmModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-2International Technology Roadmap for Semiconductors Vdd is reduced at each node to contain power consumption in spite of rising transistor density and frequency Tox is reduced to raise Ion and retain good transistor behaviors HP:High performance;LSTP:Low stand-by powerYear of Shipment20032005200720102013Technology Node(nm)9065453222Lg(nm)(HP/LSTP)37/6526/4522/3716/2513/20EOTe(nm)(HP/LSTP)1.9/2.81.8/2.51.2/1.90.9/1.60.9/1.4VDD(HP/LSTP)1.2/1.21.1/1.11.0/1.11.0/1.00.9/0.9Ion,HP(A/m)11001210150018202200Ioff,HP(A/m)0.150.340.610.840.37Ion,LSTP(A/m)440465540540540Ioff,LSTP(A/m)1e-51e-53e-53e-52e-5Strained SiliconHigh-k/Metal-GateWet LithographyNew StructureModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-37.1.2 Strained Silicon:example of innovations The electron and hole mobility can be raised by carefully designed mechanical strain.N-type SiTrenches filled with epitaxial SiGeGateSDMechanical strainModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-47.2 Subthreshold CurrentThe leakage current that flows at Vg()kTVVqtgeLWsubthresholdI/100-()SVVtgLW/10100-=nA)(h hVgsLog(Ids)Vt100W/L(nA)Vds=VddIoffWS VtL/10100-Ioff(nA)=1/SModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-8Subthreshold SwingSmaller S is desirable(lower Ioff for a given Vt).Minimum possible value of S is 60mV/dec.How do we reduce swing?Thinner Tox=larger Coxe Lower substrate doping=smaller Cdep Lower temperatureLimitationsThinner Tox oxide breakdown reliability or oxide leakage current Lower substrate doping doping is not a free parameter but set by Vt.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-9Effect of Interface States on Subthreshold SwingVg1Vg2Vg1Interface states may be filled by electrons or empty depending on its energy relative to EF,i.e.,depending on Vg.dQint/d (number or interface state per eV-cm2)presents another capacitance in parallel with Cdep Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-107.3 Vt Roll-off65nm technology.EOT=1.2nm,Vdd=1VK.Goto et al.,(Fujitsu)IEDM 2003 Vt roll-off:Vt decreases with decreasing Lg.It determines the minimum acceptable Lg because Ioff is too large if Vt becomes too small.Question:Why data is plotted against Lg,not L?Answer:L is difficult to measure.Lg is.Also,Lg is the quantity that manufacturing engineers can control directly.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-11Why Does Vt Decrease with L?Potential Barrier ConceptWhen L is small,smaller Vg is needed to reduce the barrier to 0.2V,i.e.Vt is smaller.Vt roll-off is greater for shorter L0.2VVdsEcVgs=0VVgs=Vt-longLong ChannelN+SourceN+DrainVg=0VVg=VtModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-12Vds dependenceEnergy-Band Diagram from Source to DrainL dependencelong channelVdsshort channelsource/channel barrierVgslog(Ids)Vds long channelshort channelVds=0Vds=VddVds=VddVds=0Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-13Vt Roll-off Simple Capacitance Model As the channel length is reduced,drain to channel distance is reduced Cd increasesVds helps Vgs to invert the surface,thereforeDue to built-in potential between N-channel and N+drain&source 2-D Poisson Eq.solution shows that Cd is an exponential function of L.Cdn+XjP-SubCoxeWdepToxVgsVdsModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-14 Vertical dimensions(Tox,Wdep,Xj)must be scaled to support L reductionModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-157.4 Reducing Gate-Insulator Electrical Thickness and Tunneling Leakage Oxide thickness has been reduced over the years from 300nm to 1.2nm.Why reduce oxide thickness?Larger Cox to raise IonReduce subthreshold swingControl Vt roll-offThinner is better.However,if the oxide is too thinBreakdown due to high fieldLeakage currentModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-16Gate Tunneling Leakage CurrentFor SiO2 films thinner than 1.5nm,tunneling leakage current has become the limiting factor.HfO2 has several orders lower leakage for the same EOT.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-17Replacing SiO2 with HfO2-High-k DielectricHfO2 has a relative dielectric constant(k)of 24,six times large than that of SiO2.For the same EOT,the HfO2 film presents a much thicker(albeit a lower)tunneling barrier to the electrons and holes.Toxe can be further reduced by introducing metal-gate technology since the poly-depletion effect is eliminated.(After W.Tsai et al.,IEDM03)Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-18Challenges of High-K TechnologyThe difficulties of high-k dielectrics:chemical reactions between them and the silicon substrate and gate,lower surface mobility than the Si/SiO2 systemtoo low a Vt for P-channel MOSFET(as if there is positive charge in the high-k dielectric).long-term reliabilityA thin SiO2 interfacial layer may be inserted between Si-substrate and high-k film.Question:How can Tinv be reduced?(Answer is in Sec.7.4 text)Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-197.5 How to Reduce WdepOr use retrograde doping with very thin lightly doped surface layerAlso,less impurity scattering in the inversion layer higher mobilityWdep can be reduced by increasing NsubIf Nsub is increased,Cox has to be increased in order to keep Vt the same.Wdep can be reduced in proportion to Tox.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-207.5 Ideal Retrograde Doping ProfileCompared with uniformly doped bodyAssume the body is heavily doped with an undoped layer,Trg thick,at the surface.Ideal retrograde doping yields a depletion region width(Trg)half as thick as Wdep of a uniform doped body.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-217.6 Shallow Junction and Metal Source/DrainThe shallow junction extension helps to control Vt roll-off.Shallow junction and light doping combine to produce an undesirable parasitic resistance that reduces the precious Ion.Theoretically,metal S/D can be used as a very shallow“junction”.shallow junctionextensiongateoxidedielectric spacer contact metalchannelDeep S/D silicidesilicideModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-227.6.1 MOSFET with Metal Source/Drain To unleash the potentials of Schottky S/D MOSFET,a low-Schottky junction is needed for NFETs and low-for PFET.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-237.7 Variations and Design for Manufacturing Higher Ion goes hand-in-hand with larger Ioff-think L,Vt,Tox,Vdd.Figure shows spread in Ion(and Ioff)produced by intentional difference in Lg and unintentional manufacturing variatons in Lg and other parameters.NMOSPMOSIntel,T.Ghani et al.,IEDM 2003Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-24Variation Tolerant Circuit DesignMultiple Vt Lower Vt is used only in the blocks that need speedMultiple Vdd Higher Vdd is used only in the blocks that need speedSubstrate(well)biasOnly some circuit blocks need to operate at high speed.Can use reverse well bias to raise the Vt for the rest.This techniques can also reduce the chip-to-chip and block-to-block variations with intelligent control circuitry.Would like larger body effect than conventional MOSFET.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-257.8 Ultra-Thin-Body SOI and Multigate MOSFETsReducing Tox gives the gate excellent control of Si surface potential.But,the drain could still have more control than the gate along sub-surface leakage current paths.(Right figure.)CdCgleakage pathDSCdSP-SubCgToxVgsVdsDVgsVdsModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-267.8.1 Ultra-Thin-Body MOSFET and SOIUTB MOSFET built on ultra thin silicon film on an insulator(SiO2).Since the silicon film is very thin,perhaps less than 10nm,no leakage path is very far from the gate.SourceDrainTSi=3 nmGateSiO2SiElectron Micrograph of UTB MOSFET GateN+N+SiO2Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-27Ultra-Thin-Body MOSFET The subthreshold leakage is reduced as the silicon film is made thinner.Tox=1.5nm,Nsub=1e15cm-3,Vdd=1V,Vgs=0Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-28Producing Silicon-on-Insulator(SOI)Substrates Initial Silicon wafer A and BOxidize wafer A to grow SiO2Implant hydrogen into wafer APlace wafer A,upside down,over wafer B.A low temperature annealing causes the two wafers to fuse together.Apply another annealing step to for H2 bubbles and split wafer A.Polish the surface and the SOI wafer is ready for use.Wafer A can be reused.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-29Cross-Section of SOI Circuits Due to the high cost of SOI wafers,only some microprocessors,which command high prices and compete on speed,have embraced this technology.In order to benefit from the UTB concept,Si film thickness must be agreesively reduced to Lg/4SiBuried OxideSi substrateModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-307.8.2 Multi-gate MOSFET and FinFETThe second way of eliminating deep leakage paths is to provide gate control from more than one side of the channel.The Si film is very thin so that no leakage path is far from one of the gates.Because there are more than one gates,the structure may be called multi-gate MOSFET.SourceDrainGate 1Gate 1VgToxTSiSiGate 2Gate 2double-gate MOSFETModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-31FinFET One multi-gate structure,called FinFET,is particularly attractive for its simplicity of fabrication.The channel consists of the two vertical surfaces and the top surface of the fin.Question:What is the channel width,W?Answer:The sum of twice the fin height and the width of the fin.SourceSourceDrainGateLgSOI FinFETBulk FinFETModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-32Variations of FinFET Nanowire FinFETShort FinFETTall FinFETTall FinFET has the advantage of providing a large W and therefore large Ion while occupying a small footprint.Short FinFET has the advantage of less challenging lithography and etching.Nanowire FinFET gives the gate even more control over the silicon wire by surrounding it.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-33SourceGateDrainI-V of a Nanowire“Multi-Gate”MOSFET Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-34What Parameters Determine the gds?A larger L or smaller ld,i.e.smaller Tox,Wdep,Xj,can increase the maximum voltage gain.The cause is“Vt dependence on Vds”in short channel transistors.andIdsat is a function of Vgs-Vt(From Eq.7.3.3,)dlLdsTedVdV/-=7.9 Output Conductance Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-35Channel Length Modulation For large L and Vds close to Vdsat,another mechanism may dominate gds.That is channel length modulation.Vds-Vdsat,is dissipated over a short distance next to drain,causing the“channel length”to decrease.More with increasing Vds.LVdVdsatVc=VdsatModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-367.10 Device and Process Simulation Device SimulationCommercially available computer simulation tools can solve all the equations presented in this book simultaneously with few or no approximations.Device simulation provides quick feedback about device design before long and expensive fabrication.Process SimulationInputs to process simulation:lithography mask pattern,implantation dose and energy,temperatures and times for oxidization and annealing steps,etc.The process simulator generates a 2-D or 3-D structures with all the deposited or grown and etched thin films and doped regions.This output may be fed into a device simulator as input together with applied voltages.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-37Example of Process Simulation FinFET ProcessManual,Taurus Process,Synoposys Inc.The small figures only show 1/4 of the complete FinFET-the quarter farthest from the viewer.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-38Example of Device Simulation-Density of Inversion Charge in the Cross-Section of a FinFET Body The inversion layer has a significant thickness(Tch).There are more more subthreshold inversion electrons at the corners.SDGTall FinFETShort FinFETC.-H.Lin et al.,2005 SRC TECHCONModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-397.11 MOSFET Compact Modeling for Circuit Simulation For circuit simulation,MOSFETs are modeled with analytical equations.Device model is the link between technology/manufacturing and design/product.The other link is design rules.Circuits are designed A.through circuit simulations or B.using cell libraries that have been carefully designed beforehand using circuit simulations.BSIM is the first industry standard MOSFET model.It contains all the models presented in these chapters and more.Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-40Examples of BSIM Model Results Modern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-41Example of BSIM Model ResultsModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-42Example of BSIM Model ResultsModern Semiconductor Devices for Integrated Circuits(C.Hu)Slide 7-437.12 Chapter SummaryThe major component of Ioff is the subthreshold currentVt decreases with L,a fact known as Vt roll-off,caused by drain-induced barrier lowering(DIBL).Output conductance of short channel transistors
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