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TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. ATPG Introduction for IP Team TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Agenda DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q setting specific values on the primary inputs results in values on the primary outputs which indicate whether or not the internal circuitry works properly. To ensure maximum design testability, designers must employ special DFT techniques at specific stages in the development process. TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Whats Structured DFT?Structured DFT Provides systematic and automatic approach to enhancing design testability. Goal is to increase the controllability and observability of a circuit. Methods: scan design technique, which modifies the internal sequential circuitry of the design. Built-in Self-Test (BIST) method, which inserts a devices testing function within the device itself. boundary scan, which increases board testability by adding circuitry to a chip. TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Whats ATPGATPG (Automatic Test Pattern Generation) Test patterns (test vectors), are sets of 1s and 0s placed on primary input pins during the manufacturing test process to determine if the chip is functioning properly. ATE (Automatic Test Equipment) determines if the circuit is free from manufacturing defects by comparing the fault-free outputwhich is also contained in the test patternwith the actual output measured by the ATE. Goal : create a set of patterns that achieves a given test coverage. Then run it on Tester. Pass indicated no related defects exist in this chip. TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Agenda DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q that is, internally-generated signals that can clock, set, or reset flip-flops. If these signals remain uncontrollable, they could disturb sequential elements during scan shifting. Thus, the system cannot convert these elements to scan. new_clk = scan_mode? tst_clk : gen_clk TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Async Reset Test Logic Added to Control Asynchronous Reset use ipt_async_se to control the mux. new_rst = ipt_se_async_xxx? ext_rst : int_rst TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Async Reset (2) For the case where both set and reset of a flop are internally generated, either set or reset shall be disabled during scan mode using ipt_mode_scan signal, while other can be muxed with hardreset using ipt_se_async signal. Selection of disabling set/reset signal shall be decided having less combinational logic for getting better test coverage. TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Clock GatingClock Gating When clk is pulsed from low to high, the latch is disabled and remains so as long as the clk signal stays high. Therefore, even if the output of dff1 changes from high to low as a result of the leading edge of the pulse, that value change cannot propagate through the latch and effect clk_en until clk goes low again, enabling the latch. Equally important, scan chains must operate correctly. You can force se to 1 in the load_unload procedure; however, it must be done before any “apply shift” statement. The se signal must be controllable to 1 from the chips primary inputs (IC pins). In IP DFT guide this se signal is connected to ipt_se_gatedclkp. TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Clock Gating (2)Clock Gating CellCPE+TE QDQ TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Agenda DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q&AWhats it? DFT Structured DFT ATPGTerminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. DFT SignalsDFT signals Ipt_mode_scan_xxx Ipt_se_xxx Ipt_se_async_xxx Ipt_se_gatedclkn/p_xxx Ipt_si/so_xxx Ipt_dbg_tck_xxx Ipt_dbg_trst_xxx Ipt_dbg_tms_xxx Ipt_dbf_tdi_xxx Ipt_dbg_tdo_xxx Please refer to Section 2.3 of TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Agenda DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q&AWhats it? DFT Structured DFT ATPGTerminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Soft IP Tasks Please refer to Section 2.1.1 of TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Soft IP to SoC Deliverables Please refer to Section 2.1.2 of TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Agenda DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q&AWhats it? DFT Structured DFT ATPGTerminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Coverage Collection Demo1. modify module.invoke file a. include the netlist you want to run fastscan b. change the top name2. modify module_fs.dofile a. change Contrsints A, B, C, D for your module3. modify module_fs.testproc a. change the alias for your module 4. modify chain_out.dofile a. add all the scan chains of your module 5. Command line: mkdir ./output ./module.invoke all the report and logfile will be put in the ./output TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Q&A TMFreescale Semiconductor Confidential and Proprietary Information. Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
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