RTC硬件电路参考

目录1、CRYSTAL MODEL2、RTC振荡电路3、CL对频率的影响4、驱动能力5、相位关系6、197KHZ的抑制7、误差分析8、layout* check list1、 CRYSTAL MODELManufacturing ProcessSBCrystalsQuartzBaronWaferAssembly MetalPackage DS / MX/ MSAssembly CeramicPackage CCQuartz Crystals in Metal Packages32K晶振与高频晶振区别：Tuning Fork vs AT-cutAT Cllt (lliickness Shear Resonuntor) Frequency Range:2 MHz to 3()MHzstandard manufactured fundamental mode.30MHz to 250MHzas high frequency fundamentals / inverted mesa crvstuls.狀琢z.SOOgW 3rd, 5th, 7th Harmonics are possible A卩plications: Clockoscilators, VCXO;I CXO, oexoTuiiig Fork (r lexure Modv Resonator) Frequency Range：10kHz to 200kHzin lundamcnlid mode.200kHz to 560kHzin ovcrtonc mode / 6.1 x fundamental mode Drive level max.1卩W Extensional mode Resonators 560kI Iz to2.1MHz A卩卩licutions: Power savings or slue卩mode crysLuls. R I C. lov 卩owcr crystulsQuartz Crystal ModelSymbol for a quartz crystalFigure: 132.768kHz01XTALEquivalent Electrical modelFigure:2CO : Shunt CapacitanceCO is the shunt capaciilance between the terminals, it is the sum of the electrode and the package capacitance.Fundamental modeL1 : Motional Inductance C1 : Motional CapacitanceR1 : Motional ResistanceOvertone modeL1o : Motional InductanceC10 : Motional CapacitanceR1o : Motional Resistance通过等效电路知道32K的音插型晶体其实是存在两个谐振频率，一个是 32K,另一个是197K。但厂家开始时没有提供上面的等效电路，而是只说明 存在一个32K的谐振点。在SC6600D上很容易出现197KHZ，直怀疑是否芯 片造成的。通过用下面的测试，验证了在没有芯片的前提下RTC电路的频 率响应，发现电路出现两个谐振点。后来与厂商沟通后，他们才给了更为 详细的等效电路。当然也并不是和芯片完全没关系，因为D芯片的驱动能力 加强了，所以它的输出电阻变小了，它的影响在第6节中解释。2、RTC振荡电路式（i）GMOrn荡电路在进入稳定振荡的情况下，其 AF =1的复数可进一步用模和相角表示为将模与相角分开，则有V + V = 2 n 冗AFCL=Cg*Cd/(Cg+Cd) +Cs+Cic谐振回路CRYSTAL振荡条件为2）(n = 0,1,2,3,)3、CL对频率的影响+ jxjxfrequencywhich is connected.lcHIHx a一* - jxCL =C1 C2 /注：+ CS + CIoutpuice, Ct eapac1 = C2 =|tanceCapacitorfrequencyfrequency频率的计算：第6页共17页3/28/2013Pulling sensitivityThe sensitivity of the working frequency to small changes in CL is given by:This formula shows the direct dependence of “S“ to C1. For high frequency crystals of fundamental modes “S“ can be higher than -20 ppm/pF especially for low CL values . For high over-tone orders the sensitivity is lower than for fundamental mode units, because of much lower typical C1 values.ppm/pF50-40-30-x: Ci 二 20 fF: Co 二 4.8 pF o: Ci = 10 fF: Co = 2A pF上图可以看到不同的CL规定值（通常典型值为7pf、9pf、12.5pf），对应的频率 变化灵敏度是不同的 反。很显然如果我们的芯片1、调试时较低的灵敏度 可以减少由Cg斗Cd 5%误差、PCB板以及芯片杂散电容的不一致CL值时相同的dCL影响频率可变范围要大，大CL值则相 允许的话，选用大的CL值是更有利的。因为 频率范围；可以更容易组合Cg Cd逼近所需要2、性引起频率偏差。从上图也可以看到，F1是小于32.768khz的，用户需要的是FL例如某个具体的晶体(MS2V-T1S型)的参数如下：MS2V-T1SExample of a32.768 kHzCrystal Specification：cL:12*5 pFl olcrancc:+/- 30 ppmExample of a Crystal Listing:R1 kOhrnFi kHzClfFDFl |PPm|CO1 IpFIP IW|39.684(32.765572.25+9.9.861.037下面的图将更直观的解释CL (9pf)对频率的影响。Chart of AFl dependend on CL; bad match327303277932778327773277632775327743277332772327713277032769327683276732766327653276432763327623276132760FFea ueicv FffeciiveL Cl.depen deniLO3Citan出、Fr?quericy、Shift p(inn、n-29.77Ft,rtpeinFftfge12345678910111112131415161718 H9 203603303002702402101B0150120906030-30-60-90-120-1&0-210Loadcapacitance JpFJ327703276332761327&Q3276932763针对 SP7100A vi.o.i 测试：结果 10PF+18PFSP7100A V1.0.1 (测试 5PCS) CL=9PFf(arm clk)2004.9.14RfRdCg(PF)Cd(PF)C/3.6V3.8Vppm4.0V5.1MIK12156.6732767.9932768032768. 022265.1MIK10186.4332768.0332768.0531.6232768.085.1M1K12156.6732768.0432768.092.7532768.12295.1M1K10186.4332768.1332768.1534.6732768.175.1M1K1015632768.432768.4313.132768.452055.1M1K10186.4332768.1232768.1243.7832768.175.1M1K1015632768.4332768.5215.932768.552315.1M1K10186.4332768.2232768.257.6332768.35.1M1K1015632768.332768.3310.132768.392345.1M1K10186.4332768.0332768.072.1432768.09SM5100B vl32 结果：12PF+18PFSM5100B 60pin v1.321pf探头测试Cg+Cd2+1515+2715+2215+1815+1512+18model3.6V4V3.83.8V232770.8232771.0132770.91一一一32767.9832768.1332770.6232770.8232770.74一一一32767.81432770.8232771.1132770.94一一一32768.0132768.1532770.7932771.0132770.88一一一32767.9932768.15832770.9132771.0232771.0132767.5132767.6232767.7732768.0132768.08注：经对比，1PF的探头对频率影响为降低0.1HZ左右。4、 驱动能力：* Oscillation requirementCrystal 1 Circuit fe IC* For stable oscillationRecommend at least 5 times of ReLe fe IRe = Resoname巳 resistance -R = Negative resistanceCdf(ARM CLK)从上图是负阻振荡的原理，测量方法可以用下图的办法，通过调节RX的值（即 增大RE），使电路处于临界振荡点来求得|-R|。Oscillation allowanceOscillation Allowance or Safety Margin for Pierce OscillatorResistor Rx is placed in series to the crystal.Safety margin,this is the measured Rx value where the oscillation stm件合 / stops.Oscillation allowance,is safety margin plus the ESR of the used crystal. This represents the highest ESR value were any crystal will oscillate at 25C at the given power supply.Definition of the crystaPs ESR.The typ ESR (R1 or Rs serie resistance) of the crysta should be defined 5 times smaller than the oscillation allowance.The osc nation allowance depends on the electrical characteristics of the Inverter, mainly the gain. Lower power supply, higher load-capacitance will reduce the oscillation allowanceThe safety margin is used to compensate the negative influence of in creasing ambie nt temperature on IC 白 ntJ &祐I J唱 苗宕 QMuStion to崎rances of the IC.5M100k5M100kSC8800 handse t EVT V1.0.1RfRdRxCgCdf10M220K010PF15PF32767.82hz10M220K330K10PF15PF32770hz10M220K430K10PF15PF32770hz10M220K660K10PF15PF32771hz10M220K1M10PF15PF05M 100k100k133k151k12PF12PF12PF18PF18PF18PF32768. 04hz32768. 04hz0测试结果是SC6600B的驱动负阻=133K+50K=180Kohms左右 SC8800 的驱动负阻660K+50K=710Kohms此数据及电路是对确定了参数后的电路进行的测量。晶振等效阻抗为50Kohms, 厂家建议的驱动能力应该是5倍于晶振等效阻抗，很显然我们B芯片的驱动能力不 够，而厂家没有更小的等效阻抗的晶振。鉴于此，而且B芯片中197KHZ不容易出 现，建议RD沿用IKohms，并对更多的手机进行测试，防止出现不起振现象。6、60Ch4-Ch1 相位p 197KHZ两正常的。但对197KHZ进A: 10.0mV10.OmVm所以我们i这两个频率上都也可能并并且是的是 2KMZ，而.的是而不是0.0UW0.电路抑制方法Overtone-Mode suppressionOvertone, or the 1st harmonic mode For tuning fart crystal its atHUS 1 k higher itian the fundamentai mode. AT-tut crystals have a 3W, 5m b 7th harmcmics.press ion. The resiSior 只口 togelher with I Dad-capacitor Co forms3 Jow pass filter, 220kOhm usually is safe If this r(?呂曲。唱 needed depends on lhe phase-shift characteristics of the used invertef at the fundamental and the上图通过RD和CD构成的低通滤波来抑制197KHZ。下图是构建的仿真图 Micro Crystal can perfonn this tesr 阳you a nninimum value fx the resistor R& is given which guarantees a hjndarnentabmoae osallghpnjwift w(xst-case crystal parsmeters.v6kVA11795.3386h 2f 50k1K和220K的频率响, 1|_ 904.6534h Q 7f1. OV0.8 V-0.6V-0.4 V0. ZV-3一 口KHrOk7k7RfRdCgCdf5M100K151832K5M100K151532K,偶尔 197K5M100K158.2197K nv ；H 1. OKHs丄 OrQisSOJQizlOOJQizSOOJQiz10M100K151532K10M100K151232K10M100K158.232K,偶尔 197K从上表的测试数据中可以看出另外把RF从5M变为10M,也有助于对 197KHZ的抑制。7、误差分析：1 )温度造成的频率偏差 厂家参数：Freauency vs temperature :-0.035ppm/(T-T0)八2+/- 10%实际测量:sp7100A V1.01ppm10+18pf28 C32768.1243.78417968810+18pf40 C32767.97-0.91552734410+18pf44 C32767.777.01904296910+18pf55 C32767.1-27.4658203110+18pf-22 C32766.1-57.983398442)其它晶振特性a)Frequency tolerance +/- 20 ppm b) Aging first year max +/-3ppm3) 匹配电容：由于晶振本身存在+/-20PP M的误差，即没有一个准确的参考点，所以并不确 定调试的CL 一定满足厂家要求，只能通过更多的测量数据，取平均值接近要求 的CL。另外，电容使用的是+/-5%精度的，同样存在误差，经过计算，由于电容本 身+/-5%的误差造成的频率误差在+/-1PPM左右，可以忽略。综合各种误差，尽量使常温下调整的RTC频率比32.768khz偏快几个PPM (如32.768132.7682 khz)，可以补偿温度引起的频率下偏，并且对用 户来说，假如不准，那偏快总是比偏慢的好。8、 layoutLayout ConsiderationsDue to the low-power operation of such tuning-fork,special attention should be paid on the PCB layout1、Traces: - as short as possible-avoid routing on inner layers-avoid vias2、3、干扰。不利的。内层走线必然要过孔，而且内层的杂散电容将变大。环地最好，因为RTC时钟始终在跑且电流很弱，几个uA左右，容易受GND Guard-Ring may help 感会变大，并且PCB的一致性会比较差。对怕7C 电路 CHECK LIST：1、在Cg和Cd的组合中调整频率时，尽量是Cd比Cg大一些，Rd选用大于100K, Rf选 用10 M的，这样可以加强对197KHZ的抑制2、Cg、Cd电容选用5%精度的3、在芯片驱动能力允许的情况下，应选用CL大的，如12.5pf的晶体，它对外部电容的变化的灵敏度较低，可以减少由Cg Cd 5%误差、PCB板以及芯片杂散电容 的不一致性引起频率偏差。4、尽量使常温下调整的RTC频率比32.768khz偏快几个PPM (如 32.768132.7682 khz)，可以补偿温度引起的频率下偏。5、Layout 时尽量使走线在同一层，避免过孔或走内层。6、Layout最好使RTC电路环地，减少干扰。