EDA技术发展概述

EDA技术发展概述EDA Technology Development Overview1 前言Preface人类社会已进入到高度发达的信息化社会，信息社会的发展离不开电子产品的进步。现代电子产品在性能提高、复杂度增大的同时，价格却一直呈下降趋势，而且产品更新换代的步伐也越来越快，实现这种进步的主要因素是生产制造技术和电子设计技术的发展。前者以微细加工技术为代表，目前已进展到深亚微米阶段，可以在几平方厘米的芯片上集成数千万个晶体管。后者的核心就是EDA技术，EDA是指以计算机为工作平台，融合应用电子技术、计算机技术、智能化技术最新成果而研制成的电子CAD通用软件包，主要能辅助进行三方面的设计工作：IC设计,电子电路设计,PCB设计。没有EDA技术的支持，想要完成上述超大规模集成电路的设计制造是不可想象的，反过来，生产制造技术的不断进步又必将对EDA技术提出新的要求。Human society has entered into a highly developed information society, information society development is inseparable from the progress of electronic products. Improve the performance of modern electronic products, the complexity increases, while prices have been declining, and the pace of product replacement and faster, the main factor in achieving this progress is the production of manufacturing technology and electronic design technology . The former representative of fine processing technology, has progressed to deep sub-micron stage, a few square centimeters in the chip tens of millions of transistors. The latter is the core of EDA technology, EDA refers to the computer as the work platform, the integration application of electronic technology, computer technology, intelligent technology into the latest achievements in the development of common electronic CAD software package, primarily to assist the design work in three areas: IC design, electronic circuit design, PCB design. Without the support of EDA technologies and want to complete the design and manufacture of ultra large scale integrated circuits is inconceivable, in turn, manufacturing technology continues to progress and will surely make new demands on EDA Technology2 EDA技术的发展回顾近30年电子设计技术的发展历程，可将EDA技术分为三个阶段。七十年代为CAD阶段，人们开始用计算机辅助进行IC版图编辑、PCB布局布线，取代了手工操作，产生了计算机辅助设计的概念。八十年代为CAE阶段，与CAD相比，除了纯粹的图形绘制功能外，又增加了电路功能设计和结构设计，并且通过电气连接网络表将两者结合在一起，实现了工程设计，这就是计算机辅助工程的概念。CAE的主要功能是：原理图输入，逻辑仿真，电路分析，自动布局布线，PCB后分析。九十年代为ESDA阶段，尽管CAD/CAE技术取得了巨大的成功，但并没有把人从繁重的设计工作中彻底解放出来。在整个设计过程中，自动化和智能化程度还不高，各种EDA软件界面千差万别，学习使用困难，并且互不兼容，直接影响到设计环节间的衔接。基于以上不足，人们开始追求：贯彻整个设计过程的自动化，这就是ESDA即电子系统设计自动化。2 EDA technology Recalling the past 30 years, the development process of electronic design technologies, EDA technology can be divided into three stages. Seventies for the CAD stage, people began to use computer-aided the IC layout editor, PCB layout, replacing the manual operation, resulting in a computer-aided design concept. Stage of the eighties as a CAE, compared with the CAD, in addition to pure graphics rendering features, added circuit functional design and structural design, and electrical connections through the network form the two together, to achieve the engineering design, which is The concept of computer aided engineering. CAEs main functions are: schematic entry, logic simulation, circuit analysis, automatic layout, PCB after the analysis. Nineties for the ESDA stage, although CAD / CAE technology has made tremendous success, but not the heavy design work from the thoroughly liberating. Throughout the design process, automation and intelligence level is not high, a variety of EDA software interfaces vary widely, learn to use difficult, and are not compatible, direct impact on the design aspects of the interface between. Based on the above shortcomings, people began to pursue: the automation of the process of implementing the entire design, which is is ESDA Electronic System Design Automation. 3 ESDA技术的基本特征ESDA代表了当今电子设计技术的最新发展方向，它的基本特征是：设计人员按照“自顶向下”的设计方法，对整个系统进行方案设计和功能划分，系统的关键电路用一片或几片专用集成电路(ASIC)实现，然后采用硬件描述语言(HDL)完成系统行为级设计，最后通过综合器和适配器生成最终的目标器件。这样的设计方法被称为高层次的电子设计方法，具体流程参见4.2节。下面介绍与ESDA基本特征有关的几个概念。3 ESDA basic characteristics of technology ESDA representative of todays latest developments in electronic design technology direction, and its basic features are: the designer in accordance with the top-down design approach, the whole system design and function by the systems key circuit chip with one or several specific integrated circuit (ASIC) implementation, and then using hardware description language (HDL) level design to complete system behavior, and finally through an integrated and adapters to create the final target device. This design method is called high-level electronic design methods, specific processes see Section 4.2. Here are the basic features with the ESDA related concepts. 3.1 “自顶向下”的设计方法10年前，电子设计的基本思路还是选择标准集成电路“自底向上”(BottomUp)的构造出一个新的系统，这样的设计方法就如同一砖一瓦建造金字塔，不仅效率低、成本高而且容易出错。高层次设计给我们提供了一种“自顶向下”(TopDown)的全新设计方法，这种设计方法首先从系统设计入手，在顶层进行功能方框图的划分和结构设计。在方框图一级进行仿真、纠错，并用硬件描述语言对高层次的系统行为进行描述，在系统一级进行验证。然后用综合优化工具生成具体门电路的网表，其对应的物理实现级可以是印刷电路板或专用集成电路。由于设计的主要仿真和调试过程是在高层次上完成的，这一方面有利于早期发现结构设计上的错误，避免设计工作的浪费，同时也减少了逻辑功能仿真的工作量，提高了设计的一次成功率。3.1 top down design method 10 years ago, the basic idea of electronic design or selection criteria for integrated circuits bottom-up (Bottom-Up) the construction of a new system, this design is like building the pyramids brick by brick, not only low efficiency, cost high and prone to error. High-level design provides us with a top-down (Top-Down) of the new design method, this design method first start the system design, functional block diagram in the top division and structural design. In the block diagram level simulation, error correction, and use high-level hardware description language to describe system behavior in the system level verification. Then use the integrated optimization tools to generate the specific gate netlist, the corresponding physical implementation level can be a printed circuit board or ASIC. As the design of the main simulation and debugging process is completed at a high level, this area is conducive to early detection of structural design errors, design work to avoid waste, while reducing the logic simulation of the workload and improve the design a success rate. 3.2 ASIC设计现代电子产品的复杂度日益加深，一个电子系统可能由数万个中小规模集成电路构成，这就带来了体积大、功耗大、可靠性差的问题，解决这一问题的有效方法就是采用ASIC(Application Specific Integrated Circuits)芯片进行设计。ASIC按照设计方法的不同可分为：全定制ASIC，半定制ASIC，可编程ASIC(也称为可编程逻辑器件)。设计全定制ASIC芯片时，设计师要定义芯片上所有晶体管的几何图形和工艺规则，最后将设计结果交由IC厂家掩膜制造完成。优点是：芯片可以获得最优的性能，即面积利用率高、速度快、功耗低。缺点是：开发周期长，费用高，只适合大批量产品开发。半定制ASIC芯片的版图设计方法有所不同，分为门阵列设计法和标准单元设计法，这两种方法都是约束性的设计方法，其主要目的就是简化设计，以牺牲芯片性能为代价来缩短开发时间。可编程逻辑芯片与上述掩膜ASIC的不同之处在于：设计人员完成版图设计后，在实验室内就可以烧制出自己的芯片,无须IC厂家的参与，大大缩短了开发周期。可编程逻辑器件自七十年代以来，经历了PAL、GAL、CPLD、FPGA几个发展阶段，其中CPLD/FPGA属高密度可编程逻辑器件，目前集成度已高达200万门/片，它将掩膜ASIC集成度高的优点和可编程逻辑器件设计生产方便的特点结合在一起，特别适合于样品研制或小批量产品开发，使产品能以最快的速度上市，而当市场扩大时，它可以很容易的转由掩膜ASIC实现，因此开发风险也大为降低。上述ASIC芯片，尤其是CPLD/FPGA器件，已成为现代高层次电子设计方法的实现载体。3.2 ASIC Design The complexity of modern electronic products deepening, an electronic system may consist of tens of thousands of small and medium scale integrated circuit structure, which has brought large volume, power consumption, the problem of poor reliability, effective way to solve this problem is to use ASIC (Application Specific Integrated Circuits) chip design. ASIC in accordance with design methods can be divided into: full-custom ASIC, semi-custom ASIC, programmable ASIC (also known as programmable logic devices). Design of full custom ASIC chip, the designer to define the geometry of transistors on a chip and process all the rules, the final result will be designed to mask manufactured by the IC manufacturers. Advantages are: the chip can get the best performance, that is area-efficient, high speed, low power consumption. Disadvantages are: the development cycle is long, expensive, only suitable for high-volume product development. Semi-custom ASIC chip layout are different, the design method is divided into gate arrays and standard cell design method, binding these two methods are the design method, its main purpose is to simplify the design to the expense of sacrificing chip performance shorten the development time. Programmable logic chip and the ASIC mask the difference is: the designer after the completion of layout design, in the laboratory can burn out your chip, without the involvement of IC manufacturers, greatly reducing the development cycle. Programmable logic devices since the seventies has experienced a PAL, GAL, CPLD, FPGA several stages of development, including CPLD / FPGA is a high-density programmable logic devices, the current integration has reached 2 million / film, which will cover the advantages of high integration ASIC film and design and production of programmable logic devices combined with convenient features, especially for samples or small batches of product development research to make products to market as quickly as possible, and when the market expands, it can easily transferred to the mask ASIC implementation, it also greatly reduced development risk. The ASIC chip, in particular the CPLD / FPGA devices, has become a modern high-level electronic design methods to achieve carrier. 朗读显示对应的拉丁字符的拼音3.3 硬件描述语言硬件描述语言(HDLHardware Description Language)是一种用于设计硬件电子系统的计算机语言，它用软件编程的方式来描述电子系统的逻辑功能、电路结构和连接形式，与传统的门级描述方式相比，它更适合大规模系统的设计。例如一个32位的加法器，利用图形输入软件需要输入500至1000个门，而利用VHDL语言只需要书写一行A=B+C即可，而且VHDL语言可读性强，易于修改和发现错误。早期的硬件描述语言，如ABELHDL、AHDL，由不同的EDA厂商开发，互不兼容，而且不支持多层次设计，层次间翻译工作要由人工完成。为了克服以上不足，1985年美国国防部正式推出了VHDL(Very High Speed IC Hardware Description Language)语言，1987年IEEE采纳VHDL为硬件描述语言标准(IEEE STD-1076)。VHDL是一种全方位的硬件描述语言，包括系统行为级、寄存器传输级和逻辑门级多个设计层次,支持结构、数据流、行为三种描述形式的混合描述，因此VHDL几乎覆盖了以往各种硬件描述语言的功能，整个自顶向下或自底向上的电路设计过程都可以用VHDL来完成。VHDL还具有以下优点：(1)VHDL的宽范围描述能力使它成为高层次设计的核心，将设计人员的工作重心提高到了系统功能的实现与调试，而化较少的精力于物理实现。(2)VHDL可以用简洁明确的代码描述来进行复杂控制逻辑的设计，灵活且方便，而且也便于设计结果的交流、保存和重用。(3)VHDL的设计不依赖于特定的器件，方便了工艺的转换。(4)VHDL是一个标准语言，为众多的EDA厂商支持，因此移植性好。3.3 Hardware Description Language Hardware description language (HDL-Hardware Description Language) is an electronic system for designing hardware computer language, which means using software programming to describe the logic function of an electronic system, circuit and connection forms, and the gate-level description of the traditional way compared, it is more suitable for large-scale system design. For example, a 32-bit adder, the use of graphical input software will need to enter 500-1000 doors, and use of VHDL language need only write one line to A = B + C, and VHDL, readable, easy to modify, and find errors. The early hardware description language, such as ABEL-HDL, AHDL, developed by different EDA vendors, are not compatible, and does not support multi-level design, level translation between the work should be completed by hand. To overcome the above shortcomings, the U.S. Department of Defense in 1985 launched the VHDL (Very High Speed IC Hardware Description Language) language, the adoption of IEEE 1987 VHDL hardware description language standard for the (IEEE STD-1076). VHDL is a full range of hardware description languages, including the behavior of the system level, register transfer level and gate-level multiple design levels, support structures, data flow, the behavior described in the form of a mixture of three descriptions, it covers almost the previous VHDL the function of hardware description language, the whole top-down or bottom-up process of circuit design can be done with VHDL. VHDL has the following advantages: (1) VHDL description of a wide range of high-level design capabilities make it the core focus of the design staff to improve the implementation and debugging of system functions, and of less energy in the physical implementation. (2) VHDL code can be clear and concise description of control logic to the design of complex, flexible and convenient, but also facilitate the exchange of design results, save and reuse. (3) VHDL design does not depend on a specific device to facilitate the process of conversion. (4) VHDL is a standard language for many EDA vendors support, migration is good3.4 系统框架结构EDA系统框架结构(Framework)是一套配置和使用EDA软件包的规范，目前主要的EDA系统都建立了框架结构，如Cadence公司的Design Framework，Mentor公司的Falcon Framework，而且这些框架结构都遵守国际CFI组织(CAD Framework Initiative)制定的统一技术标准。Framework能将来自不同EDA厂商的工具软件进行优化组合，集成在一个易于管理的统一的环境之下，而且还支持任务之间、设计师之间以及整个产品开发过程中信息的传输与共享，是并行工程和TopDown设计方法的实现基础。3.4 The system framework EDA system framework (Framework) is a set of configuration and use of EDA software package specification, the major EDA framework established systems, such as Cadences Design Framework, Mentors Falcon Framework, and these frames are to comply with international CFI Organization (CAD Framework Initiative) to develop uniform technical standards. Framework can come from different EDA vendors to optimize the combination of software tools, integrated in an easy-to-manage unified environment, but also to support the task between designers and the entire product development process between the information transmission and sharing, is Concurrent Engineering and Top-Down design method to achieve foundation. 朗读显示对应的拉丁字符的拼音4 EDA技术的基本设计方法EDA技术的每一次进步,都引起了设计层次上的一个飞跃,可以用图1说明4 EDA technology, the basic design Each EDA technology advances have caused a leap in the design level, you can use Figure 1 illustrates 图1 EDA技术设计层次的变化Figure 1 EDA technology design-level changes物理级设计主要指IC版图设计，一般由半导体厂家完成，对电子工程师没有太大的意义，因此本文重点介绍电路级设计和系统级设计。Mainly refers to the physical-level IC design layout, the general completed by the semiconductor manufacturers, electronic engineers do not have much meaning, so this article focuses on circuit-level design and system level design.4.1 电路级设计电路级设计工作流程如图2所示，电子工程师接受系统设计任务后，首先确定设计方案，同时要选择能实现该方案的合适元器件，然后根据具体的元器件设计电路原理图。接着进行第一次仿真，包括数字电路的逻辑模拟、故障分析，模拟电路的交直流分析、瞬态分析。系统在进行仿真时，必须要有元件模型库的支持，计算机上模拟的输入输出波形代替了实际电路调试中的信号源和示波器。这一次仿真主要是检验设计方案在功能方面的正确性。仿真通过后，根据原理图产生的电气连接网络表进行PCB板的自动布局布线。在制作PCB板之前还可以进行后分析，包括热分析、噪声及窜扰分析、电磁兼容分析、可靠性分析等，并且可以将分析后的结果参数反标回电路图，进行第二次仿真，也称为后仿真，这一次仿真主要是检验PCB板在实际工作环境中的可行性。由此可见，电路级的EDA技术使电子工程师在实际的电子系统产生前，就可以全面的了解系统的功能特性核物理特性，从而将开发风险消灭在设计阶段，缩短了开发时间，降低了开发成本。4.1 Circuit Level Design Circuit-level design flow shown in Figure 2, electronic system design engineers to accept the task, first determine the design, to achieve the same time to select the appropriate components of the program, and then the specific component design schematic. Then, a first simulation, including logic simulation of digital circuits, fault analysis, analog circuit AC and DC analysis, transient analysis. System during the simulation, the component model library must have the support of computer simulation of the input and output waveforms instead of the actual circuit debugging of the signal source and oscilloscope. This is a simulation program designed primarily to test the correctness of the function. Through simulation, according to the schematic netlist generated by electrical connection to the automatic PCB board layout. In the production of PCB board can also be used before, after analysis, including thermal analysis, noise and harassed analysis, EMC analysis, reliability analysis and the results can be analyzed against standard back to the circuit parameters, a second simulation, also known as for the post-simulation, which is mainly a simulation test PCB board in the actual work environment is feasible. Thus, the circuit-level EDA technology allows electronic engineers in the actual production of electronic systems before the system can fully understand the functional properties of the nuclear physical characteristics, which will eliminate in the design phase of development risk and shorten development time, reduce development costs. 图2 电路级设计工作流程Figure 2 circuit-level design flow 图3 系统级设计工作流程Figure 3, system-level design flow朗读显示对应的拉丁字符的拼音4.2 系统级设计进入90年代以来，电子信息类产品的开发明显出现两个特点：一是产品的复杂程度加深；二是产品的上市时限紧迫，然而电路级设计本质上是基于门级描述的单层次设计，设计的所有工作(包括设计输入，仿真和分析，设计修改等)都是在基本逻辑门这一层次上进行的，显然这种设计方法不能适应新的形势，为此引入了一种高层次的电子设计方法，也称为系统级的设计方法。高层次设计是一种“概念驱动式”设计，设计人员无须通过门级原理图描述电路，而是针对设计目标进行功能描述，由于摆脱了电路细节的束缚，设计人员可以把精力集中于创造性的方案与概念构思上，一旦这些概念构思以高层次描述的形式输入计算机后，EDA系统就能以规则驱动的方式自动完成整个设计。这样，新的概念得以迅速有效的成为产品，大大缩短了产品的研制周期。不仅如此，高层次设计只是定义系统的行为特性，可以不涉及实现工艺，在厂家综合库的支持下，利用综合优化工具可以将高层次描述转换成针对某种工艺优化的网表，工艺转化变得轻松容易。具体的设计流程见图3。4.2 System Level Design Into the 90 years since the development of electronic information products there are two significant characteristics: First, the deepening complexity of the product; the second is to market time-sensitive, but the circuit-level design is essentially based gate-level description of the single-level design, design All work (including design entry, simulation and analysis, design modification, etc.) are in the basic logic gates on this level, obviously this design method can not meet the new situation, and this introduces a high level of electronic design method, also known as system-level design. High-level design is a concept-driven design, not by the designer describes the circuit gate-level schematic, but the design goals for the function description, the details out of the shackles of the circuit, the designer can focus on creative program and the concept of the idea, once the idea of these concepts in the form of high-level description of computer input, EDA system and rule-driven approach can automatically complete the whole design. This new concept of a product can be quickly and effectively, significantly reducing product development cycle. Moreover, the definition of high-level design is just the behavior of the system may not involve implementation process, the support of the comprehensive library of manufacturers, the use of integrated optimization tools can be converted into high-level description of a process optimization for the netlist, process transformation changes too easy easy. Specific design flow shown in Figure 3. 高层次设计步骤如下：第一步：按照“自顶向下”的设计方法进行系统划分。第二步：输入VHDL代码，这是高层次设计中最为普遍的输入方式。此外，还可以采用图形输入方式(框图，状态图等)，这种输入方式具有直观、容易理解的优点。第三步：将以上的设计输入编译成标准的VHDL文件。对于大型设计，还要进行代码级的功能仿真，主要是检验系统功能设计的正确性，因为对于大型设计，综合、适配要花费数小时，在综合前对源代码仿真，就可以大大减少设计重复的次数和时间，一般情况下，可略去这一仿真步骤。第四步：利用综合器对VHDL源代码进行综合优化处理，生成门级描述的网表文件,这是将高层次描述转化硬件电路的关键步骤。综合优化是针对ASIC芯片供应商的某一产品系列进行的，所以综合的过程要在相应的厂家综合库支持下才能完成。综合后，可利用产生的网表文件进行适配前的时序仿真，仿真过程不涉及具体器件的硬件特性，是较为粗略的，一般设计，这一仿真步骤也可略去。第五步：利用适配器将综合后的网表文件针对某一具体的目标器件进行逻辑映射操作，包括底层器件配置、逻辑分割、逻辑优化、布局布线。适配完成后，产生多项设计结果：适配报告，包括芯片内部资源利用情况，设计的布尔方程描述情况等；适配后的仿真模型；器件编程文件。根据适配后的仿真模型，可以进行适配后的时序仿真，因为已经得到器件的实际硬件特性(如时延特性)，所以仿真结果能比较精确的预期未来芯片的实际性能。如果仿真结果达不到设计要求，就需要修改VHDL源代码或选择不同速度品质的器件，直至满足设计要求。第六步：将适配器产生的器件编程文件通过编程器或下载电缆载入到目标芯片FPGA或CPLD中。如果是大批量产品开发，通过更换相应的厂家综合库，可以很容易转由ASIC形式实现。 High-level design steps are as follows: The first step: In accordance with the top down design method for system division. Step two: Enter the VHDL code, which is the most common high-level design of the input. You can also use graphical input (block diagram, state diagrams, etc.), this input is intuitive, easy to understand. The third step: Enter the above design standards compiled VHDL files. For large designs, but also the code-level functional simulation, functional design mainly to test the correctness of the system, because for large-scale design, synthesis, adaptation to spend a few hours before the source code in the integrated simulation can greatly reduce design number of repetitions and time, under normal circumstances, the simulation step can be omitted. Step four: Use of integrated devices on the integrated VHDL source code optimized to generate gate-level netlist description file, which is the conversion of high-level description of the key steps in hardware. Integrated optimization is ASIC chip supplier for a particular product family, so the integrated process of the manufacturers to be integrated in the corresponding library support to complete. After synthesis can be used to generate the netlist file fit timing simulation before the simulation process does not involve specific hardware features of the device is more rough, general design, the simulation step can be omitted. Step five: After using the adapter will be integrated netlist file for a specific mapping of the target logical device operations, including low-level device configuration, logical partitions, lo