3-8译码器的VHDL设计

3 8译码器的 VHDL设计 1 实体框图 2 程序设计 正确的程序 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY DECODER38A IS PORT A2 A1 A0 S1 S2 S3 IN STD LOGIC Y OUT STD LOGIC VECTOR 7 DOWNTO 0 END ENTITY DECODER38A ARCHITECTURE ONE OF DECODER38A IS SIGNAL S STD LOGIC VECTOR 5 DOWNTO 0 BEGIN S A2 WITH S SELECT Y 11111110 WHEN 000100 11111101 WHEN 001100 11111011 WHEN 010100 11110111 WHEN 011100 11101111 WHEN 100100 11011111 WHEN 101100 10111111 WHEN 110100 01111111 WHEN 111100 11111111 WHEN OTHERS END ARCHITECTURE ONE 3 仿真波形图 4 仿真波形分析 当 S1 S2 S3 100时 只有当 A2 A1 A0 111时 Y 7 才输出低电平 否则 为高电平 当 A2 A1 A0 110时 Y 6 才输出低电平 否则为高电平 当 A2 A1 A0 101时 Y 5 才输出低电平 否则为高电平 Y 4 到 Y 0 同理 可见该程序 设计的是 3 8译码器 三 共阳极数码管七段显示译码器的 VHDL设计 1 实体框图 2 程序设计 正确的程序 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL ENTITY DISPLAY DECODER IS PORT A3 A2 A1 A0 IN STD LOGIC Y OUT STD LOGIC VECTOR 6 DOWNTO 0 END ENTITY DISPLAY DECODER ARCHITECTURE ONE OF DISPLAY DECODER IS SIGNAL S STD LOGIC VECTOR 3 DOWNTO 0 BEGIN S A3 WITH S SELECT Y1001 即大于 9 数码管无显示 由此可知 程序设计的是七段显示译码管 LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY COMPARE4 IS 四位比较器 PORT IA MORE THAN B IN STD LOGIC 高位比较的标志位的输入 IB MORE THAN A IN STD LOGIC IA EQUAL B IN STD LOGIC A IN STD LOGIC VECTOR 3 DOWNTO 0 两个输入 B IN STD LOGIC VECTOR 3 DOWNTO 0 OA MORE THAN B OUT STD LOGIC OB MORE THAN A OUT STD LOGIC OA EQUAL B OUT STD LOGIC END COMPARE4 ARCHITECTURE BEHAV OF COMPARE4 IS BEGIN PROCESS IB MORE THAN A IA EQUAL B IA EQUAL B BEGIN IF IA EQUAL B 1 THEN 从最高位比较 如果高位大则停止比较输出结果 否则进行下一位比较 IF A 3 B 3 THEN OA MORE THAN B 1 OB MORE THAN A 0 OA EQUAL B 0 ELSIF A 3 B 3 THEN OA MORE THAN B 0 OB MORE THAN A 1 OA EQUAL BB 2 THEN OA MORE THAN B 1 OB MORE THAN A 0 OA EQUAL B 0 ELSIF A 2 B 2 THEN OA MORE THAN B 0 OB MORE THAN A 1 OA EQUAL BB 1 THEN OA MORE THAN B 1 OB MORE THAN A 0 OA EQUAL B 0 ELSIF A 1 B 1 THEN OA MORE THAN B 0 OB MORE THAN A 1 OA EQUAL BB 0 THEN OA MORE THAN B 1 OB MORE THAN A 0 OA EQUAL B 0 ELSIF A 0 B 0 THEN OA MORE THAN B 0 OB MORE THAN A 1 OA EQUAL B 0 ELSE 如果输入中两个数相等的标志位为 0 则表明高位不相等 停止比较 输出结果 OA MORE THAN B 0 OB MORE THAN A 0 OA EQUAL B 1 END IF ELSE OA MORE THAN B IA MORE THAN B OB MORE THAN A IB MORE THAN A OA EQUAL B IA EQUAL B END IF END PROCESS END BEHAV LIBRARY IEEE USE IEEE STD LOGIC 1164 ALL USE IEEE STD LOGIC UNSIGNED ALL ENTITY comparator IS PORT CLK IN STD LOGIC SIN IN STD LOGIC VECTOR 3 DOWNTO 0 SJ IN STD LOGIC VECTOR 3 DOWNTO 0 Q OUT STD LOGIC END comparator ARCHITECTURE behave OF comparator IS SIGNAL SIN1 INTEGER RANGE 0 TO 15 SIGNAL SJ1 INTEGER RANGE 0 TO 15 BEGIN SIN1 CONV INTEGER SIN SJ1 CONV INTEGER SJ PROCESS CLK BEGIN IF CLK EVENT AND CLK 1 THEN IF SIN1 SJ1 THEN Q 0 ELSE Q 1 END IF END IF END PROCESS END behave