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Compact modeling with VerilogADamien QuerliozInstitut dElectronique Fondamentale, Univ. Paris-Sud, CNRS, Orsay 1 Outline What VerilogA is Two simple examples =, Verilog, Europe-VHDL For analog and mixed signal: USA - VerilogA(MS), Europe - DEPENDS 4 VerilogA vs. C Compact models used to be written in C Need to be rewritten for different simualtors Need to compute derivatievs by hand Need to write different code for DC, AC , tran analysis BUT you understand performance better BUT VerilogA can often be as fast as C today 5 A super simple exampleinclude disciplines.vamsmodule R(p,n);electrical p,n;parameter real R=5 0 .0 ;analog begin V(p,n) + R * I(p,n);endendmodule 6Could as well be I(p,n) + V(p,n)/R; A more complicated example include disciplines.vamsinclude constants.vamsmodule diode(a,c); inout a,c; electrical a,c,int; branch (a,int) res; branch (int,c) dio; parameter real is = 1 0 p from (0 :inf); parameter real rs = 0 .0 from 0 :inf); parameter real cjo = 0 .0 from 0 :inf); parameter real vj = 1 .0 from (0 :inf); real vd, id, qd; analog begin V(res) + I(res) * rs; vd = V(dio); id = is * (limexp(vd/$ vt) - 1 .0 ); if (vd vj) begin qd = cjo * vj * (1 .0 - 2 .0 * sqrt(1 .0 - vd/vj); end else begin qd = cjo * vd * (1 .0 + vd / (4 .0 * vj) ); end I(dio) + id; I(dio) + ddt(qd); endendmodule 7 =, +, = = : assigns a VARIABLE vd = V(dio); + : adds a contribution a voltage or current I(dio) + ddt(qd); = : allows to define a DIFFERENTIAL equation for a voltage or current V(n): ddt(V(n)+V(n)=V(lala); 8 How this works Every ITERATTION of the simulator, it goes thru the analog blocks: this defines the equations the simulator has to solve Highly nonlinear system The simulator will usually use iterative methods (eg Newton/Raphson) NEED DERIVATIVES OF STUFF WITH REGARDS TO VOLTAGES AND CURRENTS It will AUTOMATICALLY compute them based on the equations that you give 9 YOUR EQUATIONS SHOULD BE DERIBAVLE WITH CONTINUOUS DERIVATIVES 1 0 I V I VSEVERE CONVERGENCE ISSUES CONVERGENCE ISSUESI V GOOD IF CAN BE DANGEROUS if (vd =0 ) begin q=0 ; end else begin q=vdend FINE IN ALL LANGUAGES BUT NOT IN VERILOGA WILL ASSUME dq/dvd=0 FOR vd=0 ! 1 1 Other hazards with automatic derivatives SQRT has no derivative at 0 if (vd vj) begin qd = cjo * vj * (1 .0 - 2 .0 * sqrt(1 .0 - vd/vj); end else begin qd = cjo * vd * (1 .0 + vd / (4 .0 * vj) ); End IN ALL LANGUAGES = WOULD HAVE BEEN FINE BUT NOT IN VERILOGA ! 1 2 Other hazards abs has non continuous derivative log is decimal log, ln is natural log Suggestion: always add a comment to remind this when you use log or ln 1 /2 is 0 , like in C (1 .0 /2 .0 is 0 .5 ) Limexp instead of exp if you have convergence issues 1 3
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