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单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,第五章组合逻辑电路进阶设计,算术运算单元设计,ALU功能简介,ALU电路验证,逻辑运算单元设计,ALU功能简介,算术电路单元,逻辑电路单元,21,多工器,C0,A,B,S0,S1,S2,输出,功能选择,S2 S1 S0,进/借位,C,0,输出,执行动作,000,0,1,F=A+B,F=A+B+1,加法,有进位的加法,001,0,1,F=A-B,F=A-B-1,减法,有借位的减法,010,0,1,F=A,F=A+1,传递（无进位）,A加1,011,0,1,F=A,F=A-1,传递A,A减1,功能选择,S2 S1 S0,输出,执行动作,100,F=A,B,A与B相与,101,F=A,B,A与B相或,110,F=A xor B,A与B相异或,111,F=/A,A取反,Entity的定义,Architechture的描述,结构风格,优点,缺点,适用场合,已知条件,结构性描述,Structure,联机关系清,晰明了电路,模块化清楚,电路不易理,解繁琐、复,杂,电路的层阶化（Hierarchy）设计、PCB设计,电路规模较大且有大量模块,数据流设计,Data Flow,布尔函数定,义明白设计,快速,不易描述复,杂电路维护,及修改不易,小门数的电路设计、电路中各模块间的分散逻辑,布尔方程,行为化描述,Behavior,电路特性的,行为描述清,楚明了易于,维护,电路合成的,结果难以控,制,大型复杂的电路模块设计,流程图、,真值表,信号名称,信号模式,位数,数据类型,A,B,Cin,BCDout,Cout,输入数值1,输入数值2,输入：从前级来的进位,输出：运算结果，A+B,输出：运算后产生的进位,4,4,1,4,1,UNSIGNED,UNSIGNED,STD_LOGIC,STD_LOGIC_VECTOR,STD_LOGIC,2.算术运算单元设计,ENTITY adder IS,PORT(A:IN UNSIGNED(3 DOWNTO 0);,B:IN UNSIGNED(3 DOWNTO 0),Cin:IN STD_LOGIC;,BCDout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0),Cout:OUT STD_LOGIC,);,END adder;,library IEEE;,use IEEE.std_logic_1164.all;,use IEEE.std_logic_arith.all;,use IEEE.std_logic_unsigned.all;,entity CH5_2_1 is,port,(A:in UNSIGNED(3 downto 0);,B:in UNSIGNED(3 downto 0);,Cin:in STD_LOGIC;,S:in STD_LOGIC_VECTOR(2 downto 0);,BCDout:out STD_LOGIC_VECTOR(3 downto 0);,Cout:out STD_LOGIC,);,end CH5_2_1;,architecture ARCH of CH5_2_1 is,SIGNAL C,Y:STD_LOGIC_VECTOR(3 downto 0);,BEGIN,PROCESS(S),BEGIN,-*ADDER*,case S is,when 000=,Y(0)=A(0)XOR B(0)XOR Cin;,C(0)=(A(0)AND B(0)OR(B(0)AND Cin)OR(A(0)AND Cin);,GEN1:FOR I IN 1 TO 3 LOOP,Y(I)=A(I)XOR B(I)XOR C(I-1);,C(I)=(C(I-1)AND A(I)OR(C(I-1)AND B(I)OR(A(I)AND B(I);,END LOOP;,BCDout=Y(3),Cout -SUB;,Y(0)=A(0)XOR B(0)XOR Cin;,C(0)=(Cin AND NOT A(0)OR(Cin AND B(0)OR(NOT A(0)AND B(0);,GEN2:FOR I IN 1 TO 3 LOOP,Y(I)=A(I)XOR B(I)XOR C(I-1);,C(I)=(C(I-1)AND NOT A(I)OR(C(I-1)AND B(I)OR(NOT A(I)AND B(I);,END LOOP;,BCDout=Y(3),Cout -TRANSFER A+Cin,IF Cin=0 THEN,BCDout =A(3),ELSE,BCDout -TRANSFER A-Cin;,IF Cin=1 THEN,BCDout =A(3),ELSE,BCDout =A-1;,END IF;,Cout,BCDout=0000;,Cout,Y(3)=A(3)and B(3);,Y(2)=A(2)and B(2);,Y(1)=A(1)and B(1);,Y(0)=A(0)and B(0);,BCDout,Y(3)=A(3)or B(3);,Y(2)=A(2)or B(2);,Y(1)=A(1)or B(1);,Y(0)=A(0)or B(0);,BCDout,Y(3)=A(3)XOR B(3);,Y(2)=A(2)XOR B(2);,Y(1)=A(1)XOR B(1);,Y(0)=A(0)XOR B(0);,BCDout,Y(3)=NOT A(3);,Y(2)=NOT A(2);,Y(1)=NOT A(1);,Y(0)=NOT A(0);,BCDout,BCDout-ADDER;,Y(0)=A(0)XOR B(0)XOR Cin;,C(0)=(A(0)AND B(0)OR(B(0)AND Cin)OR(A(0)AND Cin);,GEN1:FOR I IN 1 TO 3 LOOP,Y(I)=A(I)XOR B(I)XOR C(I-1);,C(I)=(C(I-1)AND A(I)OR(C(I-1)AND B(I)OR(A(I)AND B(I);,END LOOP;,BCDout=Y(3),Cout -SUB;,Y(0)=A(0)XOR B(0)XOR Cin;,C(0)=(Cin AND NOT A(0)OR(Cin AND B(0)OR(NOT A(0)AND B(0);,GEN2:FOR I IN 1 TO 3 LOOP,Y(I)=A(I)XOR B(I)XOR C(I-1);,C(I)=(C(I-1)AND NOT A(I)OR(C(I-1)AND B(I)OR(NOT A(I)AND B(I);,END LOOP;,BCDout=Y(3),Cout -TRANSFER A+Cin;,IF Cin=0 THEN,BCDout =A(3),ELSE,BCDout =A+1;,END IF;,Cout -TRANSFER A-Cin;,IF Cin=1 THEN,BCDout =A(3),ELSE,BCDout =A-1;,END IF;,Cout -AND;,Y(3)=A(3)and B(3);,Y(2)=A(2)and B(2);,Y(1)=A(1)and B(1);,Y(0)=A(0)and B(0);,BCDout=Y(3),Cout -OR;,Y(3)=A(3)or B(3);,Y(2)=A(2)or B(2);,Y(1)=A(1)or B(1);,Y(0)=A(0)or B(0);,BCDout=Y(3),Cout -XOR;,Y(3)=A(3)XOR B(3);,Y(2)=A(2)XOR B(2);,Y(1)=A(1)XOR B(1);,Y(0)=A(0)XOR B(0);,Q=Y(3),BCDout=Y(3),Cout -NOT;,Y(3)=NOT A(3);,Y(2)=NOT A(2);,Y(1)=NOT A(1);,Y(0)=NOT A(0);,BCDout=Y(3),Cout,BCDout=0000;,Cout=0;,END CASE;,END PROCESS;,end ARCH;,
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