VHDL双语教学第11章

,Click to edit Master title style,Click to edit Master text styles,Second level,Third level,Fourth level,Fifth level,*,VHDL,Simulation&Synthesis,Balance of Signal Delay,Optimize of Late Arrived Signal,Late Arrived Signal,Late Arrived Signal,Multiple IF Statement,Late Arrived Signal,Late Arrived Signal(Improvement),所有能选通,b,的控制信号组合,Priority Encoded IF For Late Arrived Signals,Escape from previous 2 if,but should be caught by z=b selection,End if;,Priority Encoded IF For Late Arrived Control Signal,Late Arrived Control Signal,A(1),A(2),A(3),A(4),A(5),A(6),z,C(1),C(2),C(3),C(4),C(5),Late Arrived Control Signal(Improvement),A(1),A(2),A(3),A(4),A(5),A(6),z1,C(1),C(2),C(3),C(5),C(4),A(4),z1,z,Improved Code,Late Arrived Signal in CASE Statement(contd.),Improved Code(Schematic),VHDL Code Before Optimize(Case-When Clasue),VHDL Code After Optimize(Case-When Clasue),Merge both the C condition and the sel condition,Delay in CASE Statement(Schematic),Sel(0),Sel(1),Sel(2),Z,Delay in CASE Statement(Improvement),Sel(0),0,Sel(2),1,Sel(1),Z1,Z2,Z,Delay in CASE Statement,Sel(1)is slow,Sel(1)=1,Sel(1)=0,Improved Code,Close to final output,Long Calculation Path,Long Calculation Path(Schematic),Improved Code,Improved Code(Schematic),Decoder Using Indexing,In1_int as index,I is index,in1_int is compared in loop.,Out1(i)is accessed by variable i,Decoder Using Loop,Decoder Using Indexing vs.Loop,Multiple Inputs XOR Gate,XOR Chains(Schematic),XOR Tree,XOR Tree(Schematic),Multiplex Chain,Multiplex Chain(Schematic),Multiplex Tree,Operator in Conditional Expression,Schematic,Improved Code,Improved Code(Schematic),Unintentional Latch,Data_in Data_out,Cond_1,Unnecessary Calculation in LOOP,Coding Style For Synthesis(1),Omit,wait for XX ns;,Omit,(Q=0,after XX ns,),Using shifter register instead,D Q,D Q,D Q,Coding Style For Synthesis(2),Omit Initial Values,variable SUM:INTEGER:=0;,Using power on set/reset signal instead,D Q,R,S,Coding Style For Synthesis(3),Do not use variables for constants,Use const,Coding Style For Synthesis(4),Indenting Your Codes,Coding Style For Synthesis(5),Use std_logic,9 value,Automatically initialized to an unknown value,Easy to perform a board-level simulation,Coding Style For Synthesis(6),Do not use buffers,