逻辑设计基础课件

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,逻辑设计基础,*,第,12,章 寄存器和计数器,10/5/2024,1,逻辑设计基础,Registers and Register Transfers,Shift Registers,Design of Binary Counters,Counters for Other Sequences,Counter Design Using S-R and J-K,Summary,Outline:,10/5/2024,2,逻辑设计基础,12.1Registers and Register Transfers,图,12-1:,由,D,型触发器构成的带置数端的,4,位寄存器,10/5/2024,3,逻辑设计基础,10/5/2024,4,逻辑设计基础,Figure 12-2:Data Transfer Between Registers,10/5/2024,5,逻辑设计基础,Figure 12-3:Logic Diagram for 8-Bit Register with Tri-State Output,10/5/2024,6,逻辑设计基础,Fig 12-4:Data Transfer Using a Tri-State Bus,10/5/2024,7,逻辑设计基础,Fig12-5:N-Bit Parallel Adder with Accumulator,10/5/2024,8,逻辑设计基础,Figure 12-6:Adder Cell with Multiplexer,10/5/2024,9,逻辑设计基础,12.2 Shift Registers,Figure 12-7,10/5/2024,10,逻辑设计基础,Fig 12-8:8-Bit Serial-In,Serial-Out Shift Register,10/5/2024,11,逻辑设计基础,Fig 12-9,图,12-8,中移位寄存器的典型时序图,10/5/2024,12,逻辑设计基础,Figure 12-10:,并行输入输出的右移寄存器,10/5/2024,13,逻辑设计基础,10/5/2024,14,逻辑设计基础,Table 12-1:Shift Register Operation,10/5/2024,15,逻辑设计基础,串行输入一直为,SI=0,，,t,0,时刻,D,3,D,2,D,1,D,0,为,1011,10/5/2024,16,逻辑设计基础,Figure 12-12:Shift Register withInverted Feedback,10/5/2024,17,逻辑设计基础,12.3,二进制计数器的设计,计数器的设计过程,画出计数器的状态转换图,得到状态转换表,求出控制函数、输出函数。,画图,检查有无挂起,10/5/2024,18,逻辑设计基础,例题,1,：,T,触发器，计数值为,8(P264),10/5/2024,19,逻辑设计基础,现态,C B A,次态,C,+,B,+,A,+,触发器输入,T,C,T,B,T,A,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 0,0 0 1,0 1 1,0 0 1,1 1 1,0 0 1,0 1 1,0 0 1,1 1 1,Table 12-2 State Table for Binary Counter,10/5/2024,20,逻辑设计基础,Figure 12-14:Karnaugh Maps for Binary Counter,10/5/2024,21,逻辑设计基础,Figure 12-13:Synchronous Binary Counter,10/5/2024,22,逻辑设计基础,Figure 12-17:,可逆计数器,例题,2,：,D,触发器，计数值为,8,可逆,10/5/2024,23,逻辑设计基础,现态,C B A,次态,C,+,B,+,A,+,UD,00,10,01,11,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,0 0 0,1 1 1,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,x x x,x x x,x x x,x x x,x x x,x x x,x x x,x x x,10/5/2024,24,逻辑设计基础,得到表达式：,D,A,=A,+,=A (U+D),D,B,=B,+,=B (UA+DA),D,C,=C,+,=C(UBA+DBA),10/5/2024,25,逻辑设计基础,Figure 12-18:Binary Up-Down Counter,10/5/2024,26,逻辑设计基础,Fig 12-19ab:Loadable Counter with Count Enable,(a),例题,3,：,D,触发器组成,3,位计数器,有,Ld(,置数,),和,Ct(,计数,),(b),10/5/2024,27,逻辑设计基础,Figure 12-20:Circuit for Figure 12-19,10/5/2024,28,逻辑设计基础,Figure 12-21:State Graph for Counter,Table 12-3:State Table for Figure 12-21,12.4,其它顺序的计数器,10/5/2024,29,逻辑设计基础,现态,C B A,次态,C,+,B,+,A,+,触发器输入,T,C,T,B,T,A,0 0 0,0 0 1,0 1 0,0 1 1,1 0 0,1 0 1,1 1 0,1 1 1,1 0 0,-,0 1 1,0 0 0,1 1 1,-,-,0 1 0,1 0 0,x x x,0 0 1,0 1 1,0 1 1,x x x,x x x,1 0 1,10/5/2024,30,逻辑设计基础,Figure 12-22,10/5/2024,31,逻辑设计基础,Figure 12-23:Counter Using T Flip-Flops,10/5/2024,32,逻辑设计基础,Figure 12-24:Timing Diagram for Figure 12-23,10/5/2024,33,逻辑设计基础,Figure 12-25:,State Graph for Counter,10/5/2024,34,逻辑设计基础,Table 12-5 S-R Flip-Flop Inputs,12.5,用,SR,和,JK,型设计,Counter,10/5/2024,35,逻辑设计基础,例题,1,：,用,SR,型实现图,12-21,的计数器,(P269),10/5/2024,36,逻辑设计基础,Fig12-27:Counter of Figure 12-21 Using S-R Flip-Flops,10/5/2024,37,逻辑设计基础,(c)Logic circuit,10/5/2024,38,逻辑设计基础,Table 12-7 J-K Flip-Flop Inputs,10/5/2024,39,逻辑设计基础,例题,2,：,用,JK,型实现图,12-21,的计数器,(P275),10/5/2024,40,逻辑设计基础,Figure 12-28:Counter of Figure 12-21 Using J-K Flip-Flops,10/5/2024,41,逻辑设计基础,Figure 12-28:Counter of Figure 12-21 Using J-K Flip-Flops,10/5/2024,42,逻辑设计基础,触发器类型,输入端,Q=0,Q=1,Q,+,=0,Q,+,=1,Q,+,=0,Q,+,=1,D,型,D,0,1,0,1,T,型,T,0,1,1,0,SR,型,S R,0 X,1 0,0 1,X 0,JK,型,J K,0 X,1 X,X 1,X 0,Table 12-9,12.6,总结,10/5/2024,43,逻辑设计基础,