EDA技术P5-VHDL行为与结构描述

单击此处编辑母版标题样式,*,*,*,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,EDA,技术,VHDL,行为与结构描述,任课教师：安国臣,电子邮箱：,angch,1,VHDL,的行为描述与结构描述,Deeper at behavioral descriptions,Behavioral and Structural Descriptions in VHDL,How to write structural descriptions,An important of VHDL , the process,We will study :,进一步学习行为描述,如何进行结构描述,一个,VHDL,重要特征：进程,2,5.1 An example :an adder,加法器例子,It is a,general principle,of VHDL design that,as far as possible, the human designer,shoud,work at a,high level, and leave the low level,detail,of the circuits to the,constructed,by the synthesis tool.,VHDL,程序设计的,基本原则,就是,尽可能,地使设计者进行,顶层,设计，而将底层,具体,电路的设计留给逻辑综合工具,生成,。,sum = x + y;,Example:,Describe a 4-bit adder in VHDL,sum,，,x and y are all declared as being,SIGNED,(3 down to 0),sum,、,x,和,y,已声明为,4,位,有符号型,标准逻辑矢量,例如：用,VHDL,描述一个四位加法器,3,5.1 An example :an adder,加法器例子,The synthesis tool will then construct a circuit that fulfills this functions. If the designer gives,further restrictions,(e.g. maximum speed or minimum cost in logic gates ) then the synthesis tool will,adjust,the circuit produced in order to,obey,the constraints,as far as is possible,.,sum = x + y;,Example:,逻辑综合工具将自动生成该功能的电路。若设计者对电路设计还提出,进一步限制条件,(,如逻辑电路的最高工作速度或最低成本等,),，则逻辑综合工具将适当,调整,电路，以便,最大限度地,满足,约束要求。,4,5.1 An example :an adder,加法器例子,1,1,1,1,1,1,0,0,1,1,1,0,1,0,1,0,1,0,0,1,1,0,1,1,0,0,1,0,1,0,0,1,1,0,0,0,0,0,0,0,Carry out,Sum,Carry in,y,x,We will assume that we want to produce our own,detailed,description of an adder circuit in VHDL.,Now , the design stars with a full adder:,假设我们,要生成一个我们自己用,VHDL,描述,具体细节,的电路。,现在，从一个全加器开始设计：,Truth table for a full adder,5,5.1 An example :an adder,加法器例子,There are many possible circuits that would implement this truth table, one example :,有很多电路能实现这种真值表，例如,Circuit diagram,6,5.2 The dataflow description,（,VHDL,结构体中）,数据流,描述,7,In order to write a behavioral description, one way is simply to use the truth table.,LIBRARY,ieee,;,USE ieee.std_logic_1164.ALL;,ENTITY,fulladd,IS,PORT ( x, y,cin,: IN STD_LOGIC;,sum,cout,: OUT STD_LOGIC);,END,ENTITY,fulladd,;,ARCHITECTURE,simple_easy,OF,fulladd,IS,BEGIN,sum = 0 WHEN x = 0 AND y = 0 AND,cin,= 0 ,ELSE 1 WHEN x = 0 AND y = 0 AND,cin,= 1 ,ELSE 1 WHEN x = 0 AND y = 1 AND,cin,= 0 ,ELSE 0 WHEN x = 0 AND y = 1 AND,cin,= 1 ,ELSE 1 WHEN x = 1 AND y = 0 AND,cin,= 0 ,ELSE 0 WHEN x = 1 AND y = 0 AND,cin,= 1 ,ELSE 0 WHEN x = 1 AND y = 1 AND,cin,= 0 ,ELSE 1 WHEN x = 1 AND y = 1 AND,cin,= 1 ,为写出行为描述，一种方法就是利用真值表,5.2 The dataflow description,数据流,描述,8,cout, = 0 WHEN x = 0 AND y = 0 AND,cin,= 0 ,ELSE 0 WHEN x = 0 AND y = 0 AND,cin,= 1 ,ELSE 0 WHEN x = 0 AND y = 1 AND,cin,= 0 ,ELSE 1 WHEN x = 0 AND y = 1 AND,cin,= 1 ,ELSE 0 WHEN x = 1 AND y = 0 AND,cin,= 0 ,ELSE 1 WHEN x = 1 AND y = 1 AND,cin,= 0 ,ELSE 1 WHEN x = 1 AND y = 1 AND,cin,= 1 ,ELSE 1 WHEN x = 1 AND y = 1 AND,cin,= 1 ,END ARCHITECTURE,simple_easy,;,This is easy and obvious, but also,tedious,. We could take,inspiration,from the,gate level,design .,这种方法虽然显而易见，但太,繁琐,。我们可以从,门级,电路的设计方法得到,启发,。,5.2 The dataflow description,数据流,描述,9,LIBRARY,ieee,;,USE ieee.std_logic_1164.ALL;,ENTITY,fulladd,IS,PORT ( x, y,cin,: IN STD_LOGIC;,sum,cout,: OUT STD_LOGIC);,END ENTITY,fulladd,;,ARCHITECTURE,simple,OF,fulladd,IS,BEGIN,sum =,cin,XOR x XOR y;,cout,= ( x AND y ) OR (,cin,AND x ) OR ( y AND,cin,);,END ARCHITECTURE,simple,;,a behavioral description of the full adder,5.2 The dataflow description,数据流,描述,10,1. Local signals,Full adder circuit with the internal nodes,We give names to the,internal of the circuit (,n1, n2, n3, n4,)are the nodes of the circuit , then we are free to use them in our description.,局部信号,我们给电路的内部节点命名（如,n1, n2, n3, n4,），,那么就可以在程序中任意使用它们了。,5.2 The dataflow description,数据流,描述,11,1. Local signals,局部信号,ARCHITECTURE number3 OF,fulladd,IS,SIGNAL n1, n2, n3, n4: STD_LOGIC;,BEGIN,n1 = x XOR y;,sum =,cin,XOR n1;,n2 = x AND y;,n3 =,cin,AND x;,n4 = y AND,cin,;,cout,= n2 OR n3 OR n4;,END ARCHITECTURE number3;,the VHDL description is changed to,Local signals,n1, n2, n3 and n4,as part of the description,，,VHDL,描述变为,局部信号,n1,、,n2,、,n3,和,n4,作为描述的一部分,5.2 The dataflow description,数据流,描述,12,1. Local signals,局部信号,In order to use the local signals, we have declare that they,exist, that they are,signal, that they are of,name, and that they are of,type,.,The declaration Local signals take place,between the ARCHITECTURE,statement and the first BEGIN,，,要使用局部信号，我们必须先声明它们的,存在,、它们是,信号,、它们的,命名,、它们的,类型,。,局部信号的说明位于,ARCHITECTURE,语句和第一个,BEGIN,语句之间。,5.2 The dataflow description,数据流,描述,13,语法,8:,声明信号,格式：,SIGNAL,信号名, ,信号名, :,数据类型, : =,表达式, ;,信号是实体间动态交换数据的手段,用信号对象可以把实体连接在一起形成模块。作为一种硬件描述语言的元素,信号在硬件电路设计中具有一定的物理意义,它通常用来表示硬件电路中的一条硬件连接线。,在,VHDL,中，信号说明的范围也十分广泛,它可以在程序包、实体说明和结构体的说明部分进行说明。与常量说明十分类似,:,程序包中说明的信号可以在其所包含的任何实体和结构体中使用,;,实体说明中说明的信号可以在其对应的结构体中使用,;,结构体中说明的信号只能在本结构体中使用,.,VHDL,语言对象类语法,:=,表达式,用来对信号进行,初始赋值,它是一个可选项,赋值符号为,：,=,。注意,:,在,VHDL,语言程序中,信号赋值的符号与此不同,它应为,=.,5.2 The dataflow description,数据流,描述,14,赋值,运算符,3:,信号赋值符号,:=,表达式：,y := a,对,singal,（信号）赋初始值（一般在信号声明语句中） 。,对,VARIABLE,（变量），,CONSTANT,（常量）赋值，,a,赋予,y,对,GENERIC(,类属）参量赋值,这种赋值是针对表现为存储器的量，不是电路互联节点量，所以对,singal,只是赋初值用。,立即发生，对后面的语句可直接有作用。,运算符类语法,5.2 The dataflow description,数据流,描述,15,2. Concurrent processing,Lets Consider the two descriptions,并发处理,我们观察这两个描述。,ARCHITECTURE nu3 OF,fulladd,IS,SIGNAL n1, n2, n3, n4: STD_LOGIC;,BEGIN,n1 = x XOR y;,sum =,cin,XOR n1;,n2 = x AND y;,n3 =,cin,AND x;,n4 = y AND,cin,;,cout,= n2 OR n3 OR n4;,END ARCHITECTURE nu3;,ARCHITECTURE nu4 OF,fulladd,IS,SIGNAL n1, n2, n3, n4: STD_LOGIC;,BEGIN,sum =,cin,XOR n1;,cout,= n2 OR n3 OR n4;,n1 = x XOR y;,n2 = x AND y;,n3 =,cin,AND x;,n4 = y AND,cin,;,END ARCHITECTURE nu4;,They are the same as running it?,它们的执行结果一样吗？,5.2 The dataflow description,数据流,描述,16,2. Concurrent processing,并发处理,Although they are written in a,different order,they do,exactly the same thing,.,Unlike programming languages, VHDL normally monitors all statements at the same time, and executes a statement when one of its right hand side (RHS) values changes. This is called:,Concurrent,execution,虽然他们的书写顺序不同，但他们实现的功能完全相同。,不同于编程语言，,VHDL,语言同时监视所有语句，一旦某代入语句右边（,RHS,）有值的变化，就立即执行该语句，这就是所谓的：,并行执行,5.2 The dataflow description,数据流,描述,17,VHDL,语言的并行执行,HDL,用于描述,PLD,器件的硬件连接关系，所以不同于一般的编程语言。其语句有并行和顺序之分，并行语句不分先后，只要条件满足就会同时执行。,18,VHDL,的数据流,3. Dataflow VHDL,In the,jargon,of VHDL,the,style of coding,that the outputs and inputs are related through,Boolean,or,arithmetic operators,and,all statements operate concurrently, is called,dataflow,.,用,VHDL,语言的,术语,来说，输出与输入之间的关系是通过,布尔,或,算术表达式,描述的，且,所有语句都是并发执行的,，这种,代码描述方式,，被称为,数据流描述,。,5.2 The dataflow description,数据流,描述,19,结构体描述法,1,:,数据流描述法,数据流描述（,dataflow description,）是结构体描述方法之一，它描述了数据流程的运动路径、运动方向和运动结果。,when_else,：条件信号赋值语句。,with_select_when,：选择信号赋值语句。,这两种语句是数据流描述法常用的语法。,采用布尔方程，也可用数据流描述法。,结构体描述法,5.2 The dataflow description,数据流,描述,20,VHDL,（结构体中）,结构,描述,5.3,Structural VHDL,21,VHDL,结构描述,Now lets look at how to use simple design as,building blocks,to make more complex design.,Well do this building a,structural description,of a 4-bit adder.,现在，我们看看如何把简单的设计作为,构建块,，来构成更复杂的设计。,5.3,Structural VHDL,我们将如此建立,4,位加法器的,结构描述,。,22,VHDL,结构描述,5.3,Structural VHDL,1. The work library,When designs are compiled they are placed into a library ready to be used by other designs. By default,the current working library,is called,work,.,When compiled, it is added to the work library. It name within the library is:,ARCHITECTURE,simple,OF,fulladd,IS,BEGIN,sum =,cin,XOR x XOR y;,cout,x,y(2)=y,carry(2)=,cin,sum(2)=sum,carry(3)=,cout,);,c3: entity,work.fulladd(simple,),PORT MAP (x(3),y(3),carry(3),sum(3)=,sum,cout,=,coun,);,END ARCHITECTURE structural;,Continued,位置关联,名子关联,混合关联,26,VHDL,结构描述,5.3,Structural VHDL,2. Placing library components into a design,设计中的库元件调用,Each of the components that we have used is defined by a statement,provding,a,lable,for the component,the keyword,ENTITY, the,full name,of the gate, the,keword,PORT MAP, a,list,of the wires that are connected to the and output of the gate,每个被调用元件都可由包括下列各项的语句来定义：,元件标号名,关键字,ENTITY,被调元件的全称,关键字,PORT MAP,元件的输入输出连线表,这种语句称为元件,例化,（,an instantiation),27,语法,9:,元件调用语句,格式：,例化名：,ENTITY,库名,.,实体名,(,结构体名,),PORT MAP ( ,端口名,=,连接端口名，,);,例化名必须存在，相当于当前电路的一个插座名。,ENTITY,库名,.,实体名,(,结构体名,),定义了调用元件的具体路径。,PORT MAP,端口映射，说明调用元件和本实体的信号关系。,即任何一用户设计的实体，无论功能多复杂都可标准化成一个元件。,现在,EDA,工程中，把复杂的模块程序称为软核（,softcore,或,IP core,），调试仿真通过的集成电路版图称为硬核，把简单的通用模块称为元件。,它放在结构体中直接应用。,并行 语句类语法,VHDL,结构描述,5.3,Structural VHDL,28,VHDL,结构描述,5.3,Structural VHDL,3. Positional association,How do the VHDL tools know which of the wires connected to c0 are inputs and which are outputs?,c0: entity,work.fulladd(simple,),PORT MAP(x(0),y(0),cin,sum(0),carry(1);,If we compare the instantiation,with the definition of the full adder,VHDL,工具是怎么知道连接到,c0,的是那些输入和输出。,如果我们对照这个例化,和一位全加器的定义,位置关联,29,ENTITY,fulladd,IS,PORT (,x,y,cin,: IN STD_LOGIC;,sum,cout,: OUT STD_LOGIC);,END ENTITY,fulladd,;,We see that the first three signals in the port map are inputs and the last two are outputs. So the first three signals in the,instantiation,x(0),y(0),and,cin,will,be attached to,the inputs,x,y,and,cin,. Similarly,sum(0),will be connected to,sum,and,carry(1),will be connected to,cout,. This is called,positional,association,.,我们看端口映射图中前三个信号是输入端口，后两个是输出。,这样，,例化,中前三个信号,x(0),、,y(0),、,cin,将,被关联,到元件的输入,x,y,和,cin,。,以此类推,sum(0),连接到,sum,carry(1),连接到,cout,这就是,位置关联,c0: entity,work.fulladd(simple,),PORT MAP(,x(0),y(0),cin,sum(0),carry(1),);,30,VHDL,结构描述,5.3,Structural VHDL,4. Named association,Alternatively, we can explicitly say which wire is connected to which input or output of the instantiated component.,c0: entity,work.fulladd(simple,),PORT MAP (x=x(0), y=y(0),cin,=,cin,sum=sum(0),cout,=carry(1);,This is called,named,association,.,With named association, the order,doesnt matter,.,名称关联,另一种方法，就是将已经存于库中的现成元件的各个的名称分别赋予设计电路中元件的输入和输出信号。,这种映射的方法称为,名称映射法,。用名称关联与,(,书写,),顺序,无关,。,31,结构体描述法,2,:,结构化,描述法,在结构体中，通过调用库中元件（例化），实现模块化描述电路结构的方法。,无论功能多么复杂，都可以标准化成一个元件。,多层次设计的每个层次都可以作为一个元件，再构成一个模块或构成一个系统，每个元件可以分别仿真，然后再整体调试。,对于一个复杂的电子系统，可以分解成许多子系统，子系统再分解成模块。多层次设计可以使设计多人协作，并行同时进行。,结构化描述不仅是一个设计方法，而且是一种设计思想，是大型电子系统设计高层主管人员必须掌握的。,结构体描述法,VHDL,结构描述,5.3,Structural VHDL,32,语法,10:,端口映射语句,格式：,例化名,:,元件名,PORT MAP ( ,端口名,=,连接端口名, );,作用：,调用 “元件名” 这元件到本电路中，并命名为“标号名”。并说明,其引脚和本电路信号的关系。,用来实现各模块之间、各元件之间的信号连接关系映射。,其中元件名应是事先通过,COMPONENT,语句声明例化的，或元件名指定了元件所在的库、实体 、和结构体并用,ENTITY,引导如：,ENTITY,库名,.,实体名,(,结构体名,),即是,元件调用语句,并行 语句类语法,元件的端口名,调用的元件在本电路中的名称,本电路的端口名,具体的标准元件,VHDL,结构描述,5.3,Structural VHDL,有,3,种关联方式,33,VHDL,结构描述,5.3,Structural VHDL,补,1.,元件例化语句,作用与元件调用类似，是先定义某预先设计好的实体为一个元件，然后在利用端口映射语句将此元件例化，说明元件的例化名和当前电路信号的连接关系。,这种形式的元件例化，在对某元件多次调用时要方便。,元件例化语句分两部分组成：,第一部分：对一现成实体定义为一个元件。相当于对一个现成的设计实体进行封装，只留出对外的接口界面。,注意：这部分必须放在结构体的,ARCHITETURE,和,BEGIN,之间,COMPONENT,元件名,IS,GENERIC,（类属表）,PORT,（端口名表）,END COMPONENT,34,VHDL,结构描述,5.3,Structural VHDL,补,1.,元件例化语句,第二部分：将定义好的元件调用，进行端口映射，说明调用后和与当前设计实体中元件间及端口的连接关系,例化名,:,元件名,PORT MAP ( ,端口名,=,连接端口名, );,注意：这部分必须放在结构体中，可以多次使用（如电路中可使用多个加法器等电路）,同样有位置关联、,名子关联、混合关联,这两部分必须同时存在。,35,语法,11:,元件例化语句,格式：,COMPONENT,元件名,IS, GENERIC,（类属表）,PORT,（端口名表）,END COMPONENT,例化名：元件名,PORT MAP ( ,端口名,=,连接端口名，,);,类属表可列出端口的数据类型和参数, MAX+PLUSII,不支持。,PORT MAP,端口映射，说明调用元件和本实体的信号关系。,并行 语句类语法,VHDL,结构描述,5.3,Structural VHDL,在结构体中,在,ARCHITETURE,和,BEGIN,之间,36,VHDL,结构描述,5.3,Structural VHDL,USE,work.fulladd.all,-,包集合的打开,ARCHITECTURE,structural OF adder IS,COMPONENT,fulladd,IS,PORT ( x, y,cin,: IN STD_LOGIC; sum,cout,: OUT STD_LOGIC);,END COMPONENT,SIGNAL carry: STD_LOGIC_VECTOR(4 DOWNTO 0);,BEGIN,c0:,fulladd,PORT MAP (x(0),y(0),cin,sum(0),carry(1);,c1:,fulladd,PORT MAP (x(1),y(1),carry(1),sum(1),carry(2);,c2:,fulladd,PORT MAP (x(2)=x,y(2)=y,carry(2)=,cin,sum(2)=sum,carry(3)=,cout,);,c3:,fulladd,PORT MAP (x(3),y(3),carry(3),sum(3)=,sum,cout,=,coun,);,END,ARCHITECTURE structural;,用例化语句，则我们前面的结构描述可变为：,37,课堂练习,采用元件例化，调用,4,位全加器，设计,8,位全加器，,4,位全加器实体说明如下：,LIBRARY,ieee,;,USE ieee.std_logic_1164.ALL;,ENTITY adder IS,PORT ( x, y: IN STD_LOGIC_VECTOR(3 DOWNTO 0);,cin,: IN STD_LOGIC;,sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);,cout,: OUT STD_LOGIC);,END ENTITY adder;,38,课堂练习,-,参考答案,LIBRARY,ieee,;,USE ieee.std_logic_1164.ALL;,ENTITY adder8 IS,PORT ( x, y: IN STD_LOGIC_VECTOR (7 DOWNTO 0);,Cin,: IN STD_LOGIC;,Sum: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);,cout,: OUT STD_LOGIC,);,END ENTITY adder8;,39,ARCHITECTURE structural OF adder IS,COMPONENT adder IS,PORT ( x, y: IN STD_LOGIC_VECTOR(3 DOWNTO 0);,Cin,: IN STD_LOGIC;,Sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);,Cout,: OUT STD_LOGIC );,END COMPONENT;,SIGNAL carry: STD_LOGIC;,BEGIN,c0: adder PORT MAP (x =x ( 3,downto,0),y = y (3,downto,0),cin,=,Cin,sum=Sum(3,downto,0),Cout,= carry);,c1: adder PORT MAP (x =x ( 7,downto,4),y = y (7,downto,4),cin,= carry,sum=Sum(7,downto,4),Cout,=,Cout,);,END ARCHITECTURE structural;,40,进程,5.4,Processes,前面所讲结构描述法是类似原理图模式的电路结构描述,，数据流描述是类似真值表的组合逻辑描述方法，如果要实现“,沿触发,”的概念，即由,信号的变化触发,某电路的工作过程，就是进程。,这个信号对进程来说就是敏感信号。,这可实现有时间（拍）的路径概念,和同步。,41,进程,5.4,Processes,1. Sensitivity lists,ARCHITECTURE simple OF,fulladd,IS -1,BEGIN -2,cout,= ( x AND y ) OR (,cin,AND x ) OR ( y AND,cin,); -3,sum =,cin,XOR x XOR y; -4,END ARCHITECTURE simple; -5,Statement 3 will run whenever a,right hand side,value changes. So it runs when x, y or,cin,changes.,敏感信号,Here is the VHDL dataflow code that we saw previously,这是前面看过的用数据流描述的（全加器）,VHDL,代码,每当代入,(,赋值,),符号,“,=“,右边的信号值改变时，语句,3,就将被执行。,即当,x,、,y,、,cin,变化时,42,进程,5.4,Processes,1. Sensitivity lists,In the jargon of VHDL, statement 3 is,sensitive,to signals x, y,cin,. Its,sensitivity list,is x, y,cin,. A change in a signal is called an,event,on that signal.,So statement 3 runs whenever there is an event on a signal on its,sensitivity list,.,敏感信号,用,VHDL,语言术语讲，语句,3,对信号,x, y,cin,敏感,。它的,敏感信号表,包括,x, y,cin,。（,VHDL,中）一个信号的变化称之为那个信号的,事件。,因此，只要,敏感信号表,中有一个信号事件，语句,3,就被执行。,注意：语句,3,的描述是组合逻辑电路，不是触发电路,cout,= ( x AND y ) OR (,cin,AND x ) OR ( y AND,cin,);,43,进程,5.4,Processes,1. Sensitivity lists,敏感信号,Statements 3 and 4 are,concurrent, i.e. they are both active at the same time, and are,triggered,by an event on a signal on their sensitivity lists.,cout,= ( x AND y ) OR (,cin,AND x ) OR ( y AND,cin,); -3,sum =,cin,XOR x XOR y; -4,语句,3,和语句,4,是,并行处理,的，即：它们同时都在工作着，并可被各自敏感信号表中的信号事件所,触发,。,This,approach,to writing VHDL is fine as long as our design consists of blocks whose output are always,senstive,to all of their inputs,.,如果我们的设计电路组成，是输出总一直,敏感于它们的所有输入,，那么，这是一种好的表达,方式,。,44,进程,5.4,Processes,1. Sensitivity lists,敏感信号,It is useful to be able to,explicity,say what we want the sensitivity list of a piece of code to be.,This is done by a VHDL feature called a,PROCESS,.,明确,敏感信号表（触发）去执行一段代码的，这是非常有用的（一种功能）。,这可由,VHDL,的,进程语句,实现。,45,进程,5.4,Processes,进程语句结构,2. The structure of a process,PROCESS,( sensitivity list ),BEGIN,Statement 1;,Statement 2;,Statement 3;,END PROCESS;,ARCHITECTURE ,BEGIN,Statement ;,PROCESS,( sensitivity list ),BEGIN,Statement ;,END PROCESS;,Statement;,PROCESS,( sensitivity list ),BEGIN,Statement ;,END PROCESS;,END ARCHITECTURE ,46,进程,5.4,Processes,进程语句结构,2. The structure of a process,(1) The process,waits,until it is triggered by an event on,one of,the signals in its sensitivity list.,(2) When it is triggered it executes each of the statements in its body,sequentially,.,进程一直,等待,，直到敏感信号表中,任何一个,信号事件才触发（执行）。,一旦触发，进程结构中的所有语句按,顺序,执行。,The way this works is as follows:,工作方式如下：,47,进程,5.4,Processes,进程语句结构,2. The structure of a process,(3) During execution of the process, all,signal values,are,frozen,and are not updated or changed in any way,during,the execution of the process,(4) The LHS signals all receive their new value,after,the process has,suspended,its execution.,在进程执行期间，所有,信号值,都被,冻结,，不允许以任何形式更新或改变。,进程执行,挂起,后，代入符号“,=“,左边的各个信号值才能,更新,48,进程,5.4,Processes,进程语句结构,2. The structure of a process,(5) A process can be used,anywhere,that it would be legitimate to use a line of,concurrent code,.,(6) If we use,multiple,processes within an architecture, then the processes,oprate,concurrently,with one,another,and any lines of,concurrent code,with in,architeture,.,一个进程语句可以用在,任何,地方，它将是一条合法的,并行代码,。,若一结构体中有,多个,进程语句，则进程语句,和其他进程语句,以及结构体中的其他,并行语句,都是,同时运行的,。,49,进程,5.4,Processes,进程语句结构,2. The structure of a process,VHDL description in processes,ARCHITECTURE,with_process,OF,fulladd,IS,BEGIN,PROCESS,(,x, y,cin,),BEGIN,cout,= (x AND y) OR (,cin,AND x ) OR ( y AND,cin,);,END PROCESS;,sum =,cin,XOR x XOR y;,END ARCHITECTURE,with_process,;,进程,并行语句,并行运行,1,50,进程,5.4,Processes,进程语句结构,2. The structure of a process,ARCHITECTURE with_2process OF,fulladd,IS,BEGIN,PROCESS (x, y,cin,),BEGIN,cout,= (x AND y) OR (,cin,AND x ) OR ( y AND,cin,);,END PROCESS;,PROCESS (x, y,cin,),BEGIN,sum =,cin,XOR x XOR y;,END PROCESS;,END ARCHITECTURE with_2process;,x, y,cin,有变化执行,同时运行,x, y,cin,有变化执行,2,51,进程,5.4,Processes,进程语句结构,2. The structure of a process,ARCHITECTURE OF,fulladd,IS,BEGIN,PROCESS (x, y,cin,),BEGIN,cout,= (x AND y) OR (,cin,AND x ) OR ( y AND,cin,);,sum =,cin,XOR x XOR y;,END PROCESS;,END ARCHITECTURE,all_in_one,;,x, y,cin,有变化先执行,进程结束后，,cout,、,sum,才变化,x, y,cin,有变化后执行,以上三个结构体完成的功能相同，但电路结构不同。,3,52,语法,13: Wait,语句,即等待语句，是提供给设计人员挂起一个进程或子程序顺序执行的手段。,被挂起的进程或子程序继续执行的条件可以通过下列三种不同的方法：,WAIT ON,敏感信号表；,-,等待信号变化,WAIT UNTIL,布尔表达式；,-,等待表达式为真,WAIT FOR,时间表达式；,-,等待时间到继续,程序结构类语法,进程,5.4,Processes,53,进程,5.4,Processes,WAIT,语句,3. The WAIT statement,Instead of using a sensitivity list, we can the timing of execution of a process by using a WAIT statement.,ARCHITECTURE,using_wait,OF,fulladd,IS,BEGIN,PROCES