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class exersise F=A,B,C,D(1,3,4,5,6,7,12,14,15)Use the duality,find a minimal product-of-sums expression(和之积和之积)for the following logic function F.1、先将先将F转为或与表达式，转为或与表达式，F=A,B,C,D（0，2，8，9，10，11，13）2、直接卡诺图圈零化简。、直接卡诺图圈零化简。F=（B+D）（A+B）（A+C+D）F=A,B,C,D(1,3,4,5,6,7,12,14,15)CDAB00 01 11 1000011110000000011、先将、先将F转为或与表达式，转为或与表达式，得得F=A,B,C,D（0，2，8，9，10，11，13）2、求、求F的对偶式。的对偶式。FD=A,B,C,D(2,4,5,6,7,13,15)3、FD的最简与或式为：的最简与或式为：FD=BD+AB+ACD4、FD的对偶式（的对偶式（FD）D=F。F=（B+D）（A+B）（A+C+D）CDAB00 01 11 10000111101111111F=A,B,C,D(1,3,4,5,6,7,12,14,15)21、先将F转为或与表达式，得得F=A,B,C,D（0，2，8，9，10，11，13）2、求F的反演式。F=A,B,C,D(0，2,8,9,10,11,13)3、F的最简与或式为：的最简与或式为：F=BD+AB+ACD4、F的反演式（F）=F。F=（B+D）（A+B）（A+C+D）CDAB00 01 11 10000111101111111F=A,B,C,D(1,3,4,5,6,7,12,14,15)3 C h a p t e r 6 Combinational Logic Design Practices 组合逻辑设计实践组合逻辑设计实践We will studay.n6.1 n6.2n6.4n6.5n6.6n6.7n6.8n6.9n6.10 Combinational Logic Design 6.1 Documentation Standards Documentation(文档)：(P343)n1、ciruit specification：线路的详细说明。n2、block diagram：方框图.系统的主要功 能模块及其基本互连的非正式图示说明。n3、schematic diagram：原理图.n4.bill of materials(BOM)：材料清单。n5、timing diagram：定时图(波形图)，输入、输出等波形的时间关系，包括其延时.Combinational Logic Designn6.programmable logic device(PLD)：可编程 逻辑器件。field-programmable gate array(FPGA)：现场可编程门阵列。application-specific integrated circuit(ASIC)：专用集成电路。n7、circuit description：电路描述.n8.bus：总线.在框图中总线用双线或黑线表示。总线的位数用斜杠加数字说明或总线名加方括号(例inbus31.0，inbus31:0)。6.1.1 block diagram(方框图方框图)：(P345)显示系统的输入、输出、显示系统的输入、输出、功能模块内部数功能模块内部数据通路和重要控制信号据通路和重要控制信号.BUS:(总线总线)(P344)nbus is a collection of two or more related signal lines.In a block diagram,buses are drawn with a double or heavy line.nsize denoted in the bus name INBUS31.0 or INBUS31:0).block diagramnThe flow of control and data(控制流和数据流控制流和数据流)in a block diagram should be clearly indicated.schematic diagram 原理图原理图6.1.2 Gate Symbols 逻辑门的符号逻辑门的符号A small circle,called an inversion bubble6.1.3 Signal Names and Active Levels (信号名与有效电平信号名与有效电平)(P347)nEach signal name should have an active level(有效电平有效电平)associated with it.nA signal is active high(高电平有效高电平有效)if it performs the named action or denotes the named condition when it is HIGH or 1.nA signal is active low(低电平有效低电平有效)if it performs the named action or denotes the named condition when it is LOW or 0.nAsserted(有效有效),deasserted or nagated(无效无效).6.1.3 Signal Names and Active LevelsActive lowActive highREADY-READY+ERROR.LERROR.HADDR15(L)ADDR15(H)RESET*RESETENABLEENABLEGOGO/RECEIVERECEIVETRANSMIT_LTRANSMIT Distinguish (区别区别)(P348)nsignal namesnexpressions nequations READYREADY ,READY-LREADY-L=READY 6.1.4 Active Levels for Pins 引脚的有效电平(P349)n(a)AND gate(74X08)(b)NAND gate(74X00)n(c)NOR gate(74X02)(d)OR gate(74X32)Active Levels for Pins6.1.5 Bubble-to-Bubble Logic Design “圈到圈圈到圈”的逻辑设计的逻辑设计(P351)6.1.6 Drawing Layout(布局图布局图)A complete schematic page should be drawn with system inputs on the left and outputs on the right,and the general flow of signals should be from left to right.手工画图计算机绘图6.1.6 Drawing Layout(布局图布局图)1.A multiple-page schematic usually has a“flat”structure(平面结构平面结构).2.Much like programs,schematics can also be constructed hierarchically,the“top-level”schematic.层次展开(自顶向下)6.1.9 Additional Schematic InformationnIC types type(IC型号型号)nreference designators (参考标志符参考标志符)npin numbers (引脚引脚).(P360-361)nan open-drain or open-collector output.(漏极开路或集电极开路输出漏极开路或集电极开路输出)hysteresis.(滞后滞后)n6.2 Circuit Timing(电路定时电路定时)“Timing is everything”in investing,in comedy,and yes,in digital design.6.2.1 Timing Diagrams(定时图定时图)(P363)causality 6.2.2 Propagation Delaynthe propagation delay of a signal path asthe time that it takes for a change at the input of the path to produce a change at the output of the path.nfrom LOW to HIGH(tpLH)nfrom HIGH to LOW(tpHL)6.2.3 Timing Specifications 定时规格说明定时规格说明n Maximum.最大延迟最大延迟nTypical 典型延迟典型延迟nMinimum 最小延迟最小延迟nworst-case delay 最坏情况延迟最坏情况延迟nTsetup 建立时间建立时间nThold 保持时间保持时间SETUP TIME AND HOLD TIMEnSETUP TIME：n是指在时钟沿到来之前数据从不稳定到是指在时钟沿到来之前数据从不稳定到稳定所需的时间，如果建立的时间不满稳定所需的时间，如果建立的时间不满足要求那么数据将不能在这个时钟上升足要求那么数据将不能在这个时钟上升沿被稳定的打入触发器；沿被稳定的打入触发器；SETUP TIME AND HOLD TIMEnHOLD TIME：nHOLD TIME（Th：hold time）是指数据稳定后保持的时间，如果保持是指数据稳定后保持的时间，如果保持时间不满足要求那么数据同样也不能被时间不满足要求那么数据同样也不能被稳定的打入触发器。稳定的打入触发器。Standard MSI functions 中规模集成电路Decoder 译码器译码器Encoder 编码器编码器Multiplexer 多路复用器多路复用器parity circuit 奇偶校验奇偶校验Comparator 比较器比较器Adder subtractor 加法器加法器减法器减法器使能使能输入输入编码编码输出输出编码编码映射映射6.4 decoder 译码器6.4 decoder(P384)n A decoder is a multiple-input(多输入),multiple-output(多输出)logic circuit that converts coded inputs into coded outputs,where the input and output codes are different.The input code generally has fewer bits than the output code,and there is a one-to-one mapping(一对一映射)from input code words into output code words.In a one-to-one mapping,each input code word produces a different output code word.nThe most commonly used input code is an n-bit binary code,where an n-bit word represents one of 2n different coded values.n The most commonly used output code is a 1-out-of-m code,which contains m bits,where one bit is asserted at any time.使能使能输入输入编码编码输出输出编码编码映射映射6.4 Decoder（译码器）（译码器）P384n6.4.1Binary Decoder(二进制译码器二进制译码器)nn-to-2n decodernThe most common decoder circuit is an n-to-2n decoder or binary decoder.Such a decoder has an n-bit binary input code and a 1-out-of-2n output code.6.4.1Binary Decoder(二进制译码器二进制译码器)nn-to-2n decoder2-to-4 2-to-4 decoderdecoderY0Y1Y2Y3I0I1EN使能使能输入输入编码编码输出输出编码编码映射映射n位二进制码位二进制码2n中取中取1码码 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0inputsinputsEN I1 I0outputs Y3 Y2 Y1 Y0 The truth table for The truth table for a 2-to-4 binary decodera 2-to-4 binary decoder6.4.1Binary Decoder(二进制译码器二进制译码器)nn-to-2n decoder2-to-4 2-to-4 decoderdecoderY0Y1Y2Y3I0I1ENYi=EN mi使能使能输入输入编码编码输出输出编码编码映射映射n位二进制码位二进制码2n中取中取1码码 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0inputsinputsEN I1 I0outputs Y3 Y2 Y1 Y0 The truth table for The truth table for a 2-to-4 binary decodera 2-to-4 binary decoder当输入使能端当输入使能端(EN)有效时有效时Yi=miDont care notation(无关符号无关符号)使能使能输入输入编码编码输出输出编码编码映射映射n位二进制码位二进制码2n中取中取1码码 0 X X 0 0 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0inputsinputsEN I1 I0outputs Y3 Y2 Y1 Y0 The truth table for The truth table for a 2-to-4 binary decodera 2-to-4 binary decoderDesign it!Y3=EN.I1.I0Y2=EN.I1.I0Y1=EN.I1.I0Y0=EN.I1.I02-to-4 decoder logic diagram.Example 1 :Position decoding for a 3-bit mechanical encoding disk Example 2:What is the BCD decoders structrure?I3I2I1I0ENY0Y9THE IMPORTANCE OF 74-SERIES LOGIC (P342)nwell look at commonly used 74-series ICs that perform well structured logic functions.These parts are important building blocks in a digital designers toolbox.nEven when you design for PLDs,FPGAs,or ASICs,understanding 74-series MSI functions is important.In PLD-based design,standard MSI functions can be used as a starting point for developing logic equations for more specialized functions.And in FPGA and ASIC design,the basic building blocks(or“standard cells”or“macros”)provided by the FPGA or ASIC manufacturer may actually be defined as 74-series MSI functions,even to the extent of having similar descriptive numbers.6.4.2 Logic Symbols for Larger-Scale ElementsWith respect to active levels,its important to use a consistent convention to naming the internal signals and external pins.G1G2A-LG2B-LY0-LBCY7-LA5.4.4 The 74x138 3-to-8 DecodernThe 74x138 is a commercially available MSI 3-to-8 decoder.n the 74x138 has active-low outputs.(P387)m5M5Logic diagram for the 74x138 低位低位高位高位Yi=EN miG1G2A_LG2B_LENYi_L=Yi=(EN mi)EN=G1 G2A G2B =G1 G2A_L G2B_L Y0_LY1_LY7_LY2_LY3_LY4_LY5_LY6_LENm5 74x139 Truth table?The 74x139 Dual 2-to-4 DecoderWhat is the equation for the external output signal 1Y0-L?74x139 Truth table The 74x139 Dual 2-to-4 Decoder1Y0-L=1G(1B 1A)74x139 ENF=(X,Y,Z)(0,3,6,7)=(X,Y,Z)(1,2,4,5)For decorder：Yi=EN mi If enabled，Yi=miFor Active low：Yi_L=Yi so:Yi_L=mi=MiABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138Use Decoder and logic gates to implement logic functionUse Decoder and logic gates to implement logic functionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138F+5VF=(X,Y,Z)(0,3,6,7)Yi=miActive Low：Yi_L=Yi=miUse Decoder and logic gates to implement logic functionZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VFF=(X,Y,Z)(0,3,6,7)=M1 M2 M4 M5=m1 m2 m4 m5F=(X,Y,Z)(1,2,4,5)ZYXABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VF 74x139 Truth table?Example 3:The 74x139 Dual 2-to-4 DecoderWhat is the equation for the external output signal 1Y0-L?74x139 Truth table Example 3:The 74x139 Dual 2-to-4 Decoder1Y0-L=1G(1B 1A)74x139 EN Class exerciserealize the logic function F with 3-to-8 decoder and logic gates.1.F=(X,Y,Z)(1,2,4,5)2.G=(W,X,Y,Z)(0,6,8,10)ABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138How to design the 4-to-16 decoder?6.4.4 Cascading Binary Decoders (级联二进制译码器）级联二进制译码器）(P390)N0N1N2N3EN_L+5VD0_LD7_LD8_LD15_LThinkingThinking：16outputs!16outputs!74x13874x138？Y0Y7ABCG1G2AG2BY0Y7ABCG1G2AG2BU1U2 only one chip only one chip is enabledis enabled。4 inputs4 inputs，Which one is used Which one is used as as CS(Chip CS(Chip Selection)Selection)Example 4:design the 4-to-16 decoderConsider:How to make a 5-to-32 Decoder with 3-to-8 Decoder?(思考：用思考：用74x138设计设计 5-32 译码器译码器)Consider:How to make a 5-to-32 Decoder with 3-to-8 Decoder?(思考：用思考：用74x138设计设计 5-32 译码器译码器)Control inputs of three low-order bits of a 5-bit code word (5个输入的低个输入的低3位控制输入位控制输入)Control chips of two high-order bits of a 5-bit code word (5个输入的高个输入的高2位控制片选位控制片选)Example 5:design the 5-to-32 decoderN4N3N2N1N0DEC0-7 DEC8-15 DEC16-23 DEC24-3100011011 74x139 (P391)BCD Decoder(二十进制译码器二十进制译码器)Inputs:4-bit BCD codeOutputs:1-out-of 10 CodeY0Y9I0I1I2I3多余的多余的6 6个状态如何处理？个状态如何处理？输出均无效：拒绝输出均无效：拒绝“翻译翻译”作为任意项处理作为任意项处理 电路内部结构简单电路内部结构简单二二-十十进进制制译译码码器器0 0 0 0 0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 10 1 1 1 1 1 1 1 1 11 0 1 1 1 1 1 1 1 11 1 0 1 1 1 1 1 1 11 1 1 0 1 1 1 1 1 11 1 1 1 0 1 1 1 1 11 1 1 1 1 0 1 1 1 11 1 1 1 1 1 0 1 1 11 1 1 1 1 1 1 0 1 11 1 1 1 1 1 1 1 0 11 1 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1I3 I2 I1 I00123456789Y0_L Y9_L伪伪码码任任 意意 项项6.4.8 Seven-Segment Decoders (七段显示译码器七段显示译码器)(P408)abcdefg dp公共阴极公共阴极abcdefgd pNormally use(常用的有常用的有)：Light-Emitting Diodes（LED,半导体数码管）半导体数码管）Liquid-Crystal Display（LCD,液晶数码管）液晶数码管）abcdefg dp公共阳极公共阳极nInput code:4-bit BCD 输入信号：BCD码（用A3A2A1A0表示）nOutput Code:Seven-Segment Code 输出：七段码（的驱动信号）a g 1 表示亮(On)，0 表示灭(Off)abcdefg111111011011010011111Seven-Segment Decoders(七段显示译码器)七七段段显显示示译译码码器器的的真真值值表表0 0 0 0 0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 11 1 1 1 1 1 00 1 1 0 0 0 01 1 0 1 1 0 11 1 1 1 0 0 10 1 1 0 0 1 11 0 1 1 0 1 10 0 1 1 1 1 11 1 1 0 0 0 01 1 1 1 1 1 11 1 1 0 0 1 10 0 0 1 1 0 10 0 1 1 0 0 10 1 0 0 0 1 11 0 0 1 0 1 10 0 0 1 1 1 10 0 0 0 0 0 0A3 A2 A1 A0a b c d e f g01234567891011121314156.5 Encoder ENCODER (P408)nIf the devices output code has fewer bits than the input code,the device is usually called an encoder.nProbably the simplest encoder to build is a 2n-to-n or binary encoder.encoder（编码器）（编码器）Binary encoder Y0Y1Y2I0I1I71 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0The truth table for a 8-to-3 binary decoder2ninputsnoutputsencoder（编码器）（编码器）Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7前提：任何时刻只有前提：任何时刻只有 一个输入端有效。一个输入端有效。1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0The truth table for a 8-to-3 binary decoderBinary encoder Y0Y1Y2I0I1I72ninputsnoutputsencoder（编码器）（编码器）Y0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7前提：任何时刻只有前提：任何时刻只有 一个输入端有效。一个输入端有效。Trouble:When more than One Inputs are asserted?优先级（优先级（prioritypriority）1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0The truth table for a 8-to-3 binary decoderIf multiple requests can be made simultaneously,how can the encoding device decide which?nThe solution is to assign priority to the input lines,so that when multiple requests are asserted,the encoding device produces the number of the highest-priority requestor.Such a device is called a priority encoder.(P408)6.5.1 Priority Encoders(P410 )(优先编码器)A2A1A0IDLEI7I6I5I4I3I2I1I0将将 I0I7 转换为转换为 H0H7，保证其中，任何时刻只有一个有效保证其中，任何时刻只有一个有效H7=I7H6=I6 I7H5=I5 I6 I7H0=I0 I1 I2 I6 I7A2=H4+H5+H6+H7A1=H2+H3+H6+H7A0=H1+H3+H5+H7Highest-Priority数大优先数大优先 如果没有输入有效，则如果没有输入有效，则 IDLE 为为1 IDLE=I1 I2 I6 I7Logic symbol for a generic 8-input priority encoder.(P 500-501)6.4,6.9,6.20(a)(b)
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