轨至轨运放设计课件

RAIL-to-RAIL OP AMPS轨至轨运放的设计轨至轨运放的设计RAIL-to-RAIL OP AMPS轨至轨运放的设计主要内容主要内容设计原理采用电平移位法轨至轨运放的设计采用恒定电压法实现跨导恒定的设计主要内容设计原理Op Amp ConfigurationsOp Amp ConfigurationsWhy Rail-to-Rail Differential Input Stage?Why Rail-to-Rail Differential 问题为什么要提高运放的输入信号共模范围？为什么要实现跨导的恒定？问题为什么要提高运放的输入信号共模范围？How to Obtain a Rail-to-Rail Input Common Mode Range?(a)P-type differential input stage(b)N-type differential input stageHow to Obtain a Rail-to-Rail IHow to Obtain a Rail-to-Rail Input Common Mode Range?How to Obtain a Rail-to-Rail IHow to Obtain a Rail-to-Rail Input Common Mode Range?How to Obtain a Rail-to-Rail Icombining a PMOS and a NMOS Differential pairscombining a PMOS and a NMOS Dicombining a PMOS and a NMOS Differential pairscombining a PMOS and a NMOS DiWhy is a Constant Gm needed?Why is a Constant Gm needed?Techniques for N-P ComplementaryRail-to-Rail Input Stage1.For input stages with input transistors working in weak-inversion region,using current complementary circuit to keep the sum of IN andIP constant 126;2.Using square root circuit to keep constant 31316;3.and 4.Using current switches to change the tail current of input differential pairs 3456;4.Using hex-pair structure to control the tail currents of backup pairs 7;Techniques for N-P ComplementaTechniques for N-P ComplementaryRail-to-Rail Input Stage(contd)5.Using maximum/minimum selection circuit to conduct the output current of the differential pair with larger current,as well as larger gm,to the next stage 89;6.Using electronic zener diode to keep constant 10;7.Using DC level shift circuit to change the input DC level 11.We will analyze them one by one in the following sections.There are still other techniques 1214151718,interested readers may check these references.Techniques for N-P ComplementaRail-to-Rail Input Stage,Structure 2Basic idea For an input differential pair,using a 1st order approximation,Rail-to-Rail Input Stage,StruRail-to-Rail Input Stage,Structure 3 346Using current switches to change the tail current of input differential pairsRail-to-Rail Input Stage,Stru具体电路具体电路Rail-to-Rail Input Stage,Structure 6 89Using Maximum/Minimum selection circuitRail-to-Rail Input Stage,StruThe block diagramThe block diagram最大电流选择电路最大电流选择电路Rail-to-Rail Input Stage,Structure 7Using DC shifting circuit to change the input DC levelRail-to-Rail Input Stage,Stru具体电路具体电路Rail-to-rail amplifier with Zener diodeRail-to-rail amplifier with ZeSummary and ComparisonSummary and Comparison进一步研究的问题Mismatch between N-channel andP-channel transconductorsTransition RegionCMRR degradation(40-60 dB)Nonlinearity进一步研究的问题Mismatch between N-chaReferences I1 J.F.Duque-Carrillo,J.M.Carillo,J.L.Ausin,and E.Sanchez-Sinencio,“Robust and universal constant-gm circuit technique,”Electronics Letters,vol.38,no.9,pp.396-397,Apr.2002.2 M.Wang,T.L.Mayhugh,S.H.K.Embabi,and E.Sanchez-Sinencio,“Constant-gm Rail-to-Rail CMOS Op-Amp Input Stage with Overlapped Transition Regions,”IEEE J.of Solid State Circuits,vol.34,no.2,pp.148-156,Feb.1999.3 G.Ferri and W.Sansen,“A Rail-to-Rail Constant-gm Low-Voltage CMOS Operational Transconductance Amplifier,”IEEE J.of Solid State Circuits,vol.32,no.10,pp.1563-1567,Oct.1997.4 J.Ramirez-Angulo,R.G.Carvajal,J.Tombs,and A.Torralba,“Low-Voltage CMOS Op-Amp with Rail-toRail Input and Output Signal Swing for Continuous-Time Signal Processing Using Multiple-Input Floating-Gate Transistors,”IEEE Trans.On Circuits and Systems II,vol.48,no.1,pp.111-116,Jan 2001.5 J.M.Carrillo,J.F.Duque-Carrillo,G.Torelli,and J.L.Ausin,“General Purpose rail-to-rail input circuit with constant behavior for VLSI cell libraries,”IEEE International Symposium on Circuits and Systems,vol.3,pp.607-610,May 2002References I1 J.F.Duque-CReferences II1 J.H.Huijsing,and D.Linebarger,“Low voltage operational amplifier with rail-to-rail input and output stages,”IEEE Journal of Solid-State Circuits,vol.SC-20,no.6,pp.1144-1150,December 19852 W.-C.S.Wu,W.J.Helms,J.A.Kuhn,and B.E.Byrkett,“Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges,”IEEE Journal of Solid-State Circuits,vol.29,no.1,pp.63-66,January 19943 R.Hogervorst,R.J.Wiegerink,P.A.L.de Jong,J.Fonderie,R.F.Wassenaar,and J.H.Huijsing,“CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage,”IEEE Proc.ISCAS 1992,pp.2876-28794 R.Hogervost,J.P.Tero,R.G.H.Eschauzier and J.H.Huijsing,“A compact power-efficient 3-V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries,”IEEE Journal of Solid-State Circuits,vol.29,no.12,pp.1505-1513,December 19945 R.Hogervorst,S.M.Safai,and J.H.Huijsing,“A programmable 3-V CMOS railto-rail opamp with gain boosting for driving heavy loads,”IEEE Proc.ISCAS 1995,pp.1544-15476 J.H.Huijsing,R.Hogervorst,and K.-J.de Langen,“Low-power low-voltageVLSI operational amplifier cells,”IEEE Trans.Circuits and Systems-I,vol.42.no.11,pp.841-852,November 1995References II1 J.H.HuijsiReferences(contd)7 W.Redman-White,“A high bandwidth constant gm,and slew-rate rail-to-rail CMOS input circuit and its application to analog cell for low voltage VLSI systems,”IEEE Journal of Solid-State Circuits,vol.32,no.5,pp.701-712,May 19978 C.Hwang,A.Motamed,and M.Ismail,“LV opamp with programmable rail-to-rail constant-gm,”IEEE Proc.ISCAS 1997,pp.1988-19599 C.Hwang,A.Motamed,and M.Ismail,“Universal constant-gm input-stage architecture for low-voltage op amps,”IEEE Trans.Circuits and Systems-I,vol.42.no.11,pp.886-895,November 199510 R.Hogervost,J.P.Tero,and J.H.Huijsing,“Compact CMOS constant-gm rail-to-rail input stage with gm-control by an electronic zener diode,”IEEE Journal of Solid-State Circuits,vol.31,no.7,pp.1035-1040,July 199611 M.Wang,T.L.Mayhugh,Jr.,S.H.K.Embabi,and E.Snchez-Sinencio,“Constant-gm rail-to-rail CMOS op-amp input stage with overlapped transition region,”IEEE Journal of Solid-State Circuits,vol.34,no.2,pp.148-156,February 199912 G.Ferri and W.Sansen,“A rail-to-rail constant-gm low-voltage CMOSoperational transconductance amplifier,”IEEE Journal of Solid-State Circuits,vol.32,no.10,pp.1563-1567,October 1999References(contd)7 W.RReferences(contd)13 S.Sakurai and M.Ismail,“Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage,”IEEE Journal of Solid-State Circuits,vol.31,no.2,pp.146-156,February 199614 J.H.Botma,R.F.Wassenaar,and R.J.Wiegerink,“Simple rail-to-rail lowvoltage constant transconductance CMOS input stage in weak inversion,”Electronics Letters,vol.29,no.12,pp.1145-1147,June 199315 V.I.Prodanov and M.M.Green,“Simple rail-to-rail constant transconductance input stage operating in strong inversion,”IEEE 39th Midwest Symposium on Circuits and Systems,vol 2,pp.957-960,August 199616 J.H.Botma,R.F.Wassenaar,and R.J.Wiegerink,“A low voltage CMOS op amp with a rail-to-rail constant-gm input stage and a class AB rail-to-rail output stage,”IEEE Proc.ISCAS 1993,vol.2,pp.1314-1317,May 199317 J.F.Duque-Carrillo,J.M.Valverde,and R.Perez-Aloe,“Constant-gm rail-to-railcommon-mode range input stage with minimum CMRR degradation,”IEEE Journal of Solid-State Circuits,vol.28,no.6,pp.661-666,June 199318 A.L.Coban and P.E.Allen,“A low-voltage CMOS op amp with rail-to-rail constant-gm input stage and high-gain output stage,”IEEE Proc.ISCAS 1995,vol.2,pp.1548-1551,April-May 1995References(contd)13 S.References(contd)19 T.W.Fischer,A.I.Karsilayan,and E.Snchez-Sinencio,“A Rail-to-Rail Amplifier Input Stage with+/-0.35%gm Fluctuation,”IEEE Transactions OnCircuits and Systems I.vol.52,No.2,pp271-282,February 2005.20 J.Hu,S.Yan,and E.Snchez-Sinencio,“A Constant-GM Rail-to-Rail Op Amp Input Stage Using Dynamic Current Scaling Techniques,”IEEE International Symposium on Circuits and Systems,Kobe,Japan,May 23-26,2005.21 S.Yan,J.Hu,T.Song,and E.Snchez-Sinencio,“Constant-gm Techniques for Rail-to-Rail CMOS Input Stages:A Comparative Study,”IEEE International Symposium on Circuits and Systems 2005,Kobe,Japan,May 23-26,2005.22 T.Song,J.Hu,X.Li,S.Yan and E.Snchez-Sinencio,A Robust and ScalableConstant gm Rail-to-Rail CMOS Input Stage with Dynamic Feedback for VLSI Cell Libraries,IEEE Transactions on Circuits and Systems I,pp804-816,Vol.55,Issue 3,April 2008.References(contd)一种采用电平移位法的恒跨导轨至轨运放的设计一种采用电平移位法的恒跨导轨至轨运放的设计设计指标参数名参数名 设计值设计值 电源电压（VDD）3.3v 开环增益（RL=10k，CL=10pf）80dB相位裕量（RL=10k，CL=10pf）60度单位增益带宽（RL=10k，CL=10pf）5MHz转换速度（CL=10pf）10v/us共模抑制比80dB电源抑制比80dB输入共模范围0-3.3v输出摆幅0-3.3v跨导变化率5%设计指标参数名 设计值 电源电压（VDD）3.3v 开环增轨至轨特点一、输入输出信号范围尽可能大，从Vss到Vdd。二、输入级的跨导在共模输入电压范围内基本保持恒定。轨至轨特点一、输入输出信号范围尽可能大，从Vss到Vdd。互补差分输入级1、低共模输入：PMOS饱和，NMOS截止2、高共模输入：NMOS饱和，PMOS截止3、输入级最小电源电压：Vsup=Vsgp+Vgsn+2Vdsat 4、共模输入范围为VSSVcmVDD 互补差分输入级1、低共模输入：PMOS饱和，NMOS截止PMOS/NMOS互补差分对的致命缺陷：在整个共模输入范围内，输入电路的总跨导不恒定。在两对MOS管同时导通时，其总跨导是其它部分的2倍。PMOS/NMOS互补差分对的致命缺陷：在整个共模输入范围内电平移位法恒定跨导平移PMOS对或者NMOS对的跨导曲线，使中间重合的部分正好为恒定的常数，且同非重合部分相等。PMOS对左平移法的原理图 一、原理电平移位法恒定跨导平移PMOS对或者NMOS对的跨导曲线，使 1、首先要求非重叠部分即需满足：和2、确定平移的量也就是讨论NMOS（或PMOS）对的跨导的2个转折点。1、首先要求非重叠部分即需满足：和2、确定平移的量也就是讨二、平移电路采用输入端接入共源电路的方法。利用MOS管的栅源电压来抬高或降低输入共模电压的范围从而达到平移跨导曲线的目的。这里采用的是PMOS对的左平移法。利用Mb2，Mb3，M5，M6构成共源电路来对PMOS差分对的跨导进行平移，平移的大小为二、平移电路采用输入端接入共源电路的方法。利用MOS管的栅源三、半定量分析1、NMOS管M3开始工作，得出 2、Vcm增大，直到M3，M4，Mbn都进入饱和区，得出 以上两个式子就是NMOS对的跨导 的转折点。同理，可以求出PMOS对的2个转折点，如下：3、Vcm从Vdd减小到M1开始导通得出 4、Vcm再减小时，M1，M2，Mbp进入饱和状态，得出三、半定量分析1、NMOS管M3开始工作，根据电平位移法的原理，得出以下方程式：简化后，两式相减可得出：分解为即根据电平位移法的原理，得出以下方程式：简化后，两式相减可得所以满足：这两个条件。和可知 M1和M3的宽长比之比。由可算出由得由可得出Mb2的宽长比。所以满足：这两个条件。和可知 M1和M3的宽长比之比。由可ClassAB输出级结构mosmos管工作在饱和区时管工作在饱和区时令则满足满足输出跨导恒定输出跨导恒定ClassAB输出级结构mos管工作在饱和区时令则满足输出跨Rail to RailRail to Rail电路的实际宽长比电路的实际宽长比的手工计算的手工计算从从CSMC 0.5um MIX工艺库文件中得到工艺参数工艺库文件中得到工艺参数一、输入级参数计算设设Rail to Rail电路的实际宽长比的手工计算从CSMCRail to Rail Rail to Rail 输入级实际电路图输入级实际电路图Rail to Rail 输入级实际电路图按照平移法原理的分析按照平移法原理的分析 取取则设平移电路的电流设平移电路的电流再计算再计算按照平移法原理的分析 取则设平移电路的电流再计算实际的实际的rail-to-rail输出级电路图输出级电路图则G30由前级决定为常数，确定这里设2.25v。再综合考虑为保证再综合考虑为保证M30-M31能工作在饱和区，设能工作在饱和区，设得出二、输出级参数计算实际的rail-to-rail输出级电路图则G30由前级决定中间级共源共栅电路图三、中间级共源共栅参数计算总增益中间级共源共栅电路图三、中间级共源共栅参数计算总增益根据设计指标和电路原理手工计算得出的MOS宽长比 根据设计指标和电路原理手工计算得出的MOS宽长比 Rail_To_Rail放大器放大器采用恒定电压法实现跨导恒定的设计采用恒定电压法实现跨导恒定的设计Rail_To_Rail放大器采用恒定电压法实现跨导恒结构与原理当共模信号Vicm很大时，此时只有NMOS差分对(M13,M14)导通，PMOS差分对(M11,M12)截止，此时的跨导大小为：当共模信号Vicm很小时，此时只有PMOS差分对（M11,M12）导通，NMOS差分对（M13,M14）截止，此时的跨导大小为：结构与原理当共模信号Vicm很大时，此时只有NMOS差分对(结构与原理当共模信号Vicm处于中间时，此时NMOS、PMOS差分对均会导通，此时的跨导大小为：注：这里所有的推导是假设每个管子通过的电流为4Iref 中间跨导是两边跨导的一倍结构与原理当共模信号Vicm处于中间时，此时NMOS、PMO随着共模信号的增大互补差分对的工作情况随着共模信号的增大互补差分对的工作情况解决方案保持跨导恒定的方法降低中间跨导1）减少共模信号处于中间状态时电流2）怎样控制电流使得在 处于较大以及较小的情况下分别保持NMOS、PMOS差分对中的电流保持不变4Iref 增加并联二极管支路解决方案保持跨导恒定的方法定量的计算 解之得处于中间状态时,流过NMOS、PMOS差分对中的电流为Iref而不是4Iref 二极管支路的电流为多少？定量的计算 二极管支路一是，稳压管的制作工艺与标准的CMOS工艺是不兼容的。二是，在稳压管正常工作的情况之下，如何精确的控制流过其中的电流为6显然这是很难做到的。当 处于较大时，由于NMOS差分对导通，则，PMOS差分对不导通，则 从而稳压电路是不导通的。当 处于较小时，与上面的分析同理。采用稳压管二极管支路一是，稳压管的制作工艺与标准的CMOS工艺是不兼容处于中间状态的情况此时PMOS，NMOS差分对均处于导通状态，如果没有稳压管的情况下，显然这时稳压管正常的导通。处于中间状态的情况此时PMOS，NMOS差分对均处于导通状态处于中间状态时，流过二极管支路的电流是6Iref其中由上面的假设,则 同理可知，M11的栅极G11与M16的栅极G16是等位点处于中间状态时，流过二极管支路的电流是6Iref其中由上面的管子的尺寸管子的尺寸电阻与电容电阻与电容存在的误差共模电压处于较大以及较小的情况支路有小电流MOS管导通与截止存在缓慢变化过程伏安特性非理想P管与N管非对称 如何消除？存在的误差共模电压处于较大以及较小的情况支路有小电流