Quartus常见错误分析

Quartus常用错误分析-06-15 10:031.Found clock-sensitive change during active clock edge at time on register 因素：vector source file中时钟敏感信号（如：数据，容许端，清零，同步加载等）在时钟的边沿同步变化。而时钟敏感信号是不能在时钟边沿变化的。其后果为导致成果不对的。措施：编辑vector source file2.Verilog HDL assignment warning at : truncated with size to match size of target (因素:在HDL设计中对目的的位数进行了设定,如:reg4:0 a;而默觉得32位,将位数裁定到合适的大小措施:如果成果对的,不必加以修正,如果不想看到这个警告,可以变化设定的位数3.All reachable assignments to data_out(10) assign 0, register removed by optimization因素:通过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port - changes to this connectivity may change fitting results因素:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋0，便会被接地，赋1接电源。如果你的设计中这些端口就是这样用的，那便可以不理睬这些warning5.Found pins ing as undefined clocks and/or memory enables因素:是你作为时钟的PIN没有约束信息。可以对相应的PIN做一下设定就行了。重要是指你的某些管脚在电路当中起到了时钟管脚的作用，例如flip-flop的clk管脚，而此管脚没有时钟约束，因此QuartusII把“clk”作为未定义的时钟。措施:如果clk不是时钟，可以加“not clock”的约束；如果是，可以在clock setting当中加入；在某些对时钟规定不很高的状况下，可以忽视此警告或在这里修改:AssignmentsTiming analysis settings.Individual clocks.6.Timing characteristics of device EPM570T144C5 are preliminary因素:由于MAXII 是比較新的元件在 QuartusII 中的時序并不是正式版的,要等 Service Pack措施:只影响 Quartus 的 Waveform7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled措施:将setting中的timing Requirements&Option-More Timing Setting-setting-Enable Clock Latency中的on改成OFF8.Found clock high time violation at 14.8 ns on register |counter|lpm_counter:count1_rtl_0|dffs11因素:违背了steup/hold时间，应当是后仿真，看看波形设立与否和时钟沿符合steup/hold时间措施:在中间加个寄存器也许可以解决问题9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay因素:时钟抖动不小于数据延时,当时钟不久，而if等类的层次过多就会浮现这种问题,但这个问题多是在器件的最高频率中才会浮现措施：setting-timing Requirements&Options-Default required fmax 改小某些，如改到50MHZ10.Design contains input pin(s) that do not drive logic因素:输入引脚没有驱动逻辑(驱动其她引脚）,所有的输入引脚需要有输入逻辑措施:如果这种状况是故意的,不必理睬,如果非故意,输入逻辑驱动.11.Warning：Found clock high time violation at 8.9ns on node TEST3.CLK因素：FF中输入的PLS的保持时间过短措施：在FF中设立较高的时钟频率12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew因素:如果你用的 CPLD 只有一组全局时钟时，用全局时钟分频产生的另一种时钟在布线中当作信号解决，不能保证低的时钟歪斜(SKEW)。会导致在这个时钟上工作的时序电路不可靠，甚至每次布线产生的问题都不同样。措施:如果用有两组以上全局时钟的 FPGA 芯片，可以把第二个全局时钟作为另一种时钟用，可以解决这个问题。13.Critical Warning: Timing requirements were not met. See Report window for details.因素：时序规定未满足，措施：双击Compilation Report-Time Analyzer-红色部分（如clock setup:clk等）-左键单击list path,查看fmax的SLACK REPORT再根据提示解决,有也许是程序的算法问题14.Cant achieve minimum setup and hold requirement along path(s). See Report window for details.因素：时序分析发现一定数量的途径违背了最小的建立和保持时间，与时钟歪斜有关,一般是由于多时钟引起的措施：运用Compilation Report-Time Analyzer-红色部分（如clock hold:clk等），在slack中观测是hold time为负值还是setup time 为负值，然后在：Assignment-Assignment Editor-To中增长时钟名(from node finder)，Assignment Name中增长 多时钟有关的Multicycle 和Multicycle Hold选项，如hold time为负，可使Multicycle hold的值multicycle,如设为2和1。15: Cant analyze file - file E:/quartusii/*/*.v is missing因素：试图编译一种不存在的文献，该文献也许被改名或者删除了措施：不管她，没什么影响16.Warning: Cant find signal in vector source file for input pin |whole|clk10m因素：由于你的波形仿真文献（ vector source file ）中并没有把所有的输入信号(input pin)加进去，对于每一种输入都需要有鼓励源的17.Error: Cant name logic scfifo0 of instance inst - has same name as current design file因素：模块的名字和project的名字重名了措施：把两个名字之一改一下，一般改模块的名字18.Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0因素：模块不是在本项目生成的，而是直接copy了别的项目的原理图和源程序而生成的，而不是用QUARTUS将文献添加进本项目措施：不必理睬，不影响使用19.Timing characteristics of device are preliminary因素：目前版本的QuartusII只对该器件提供初步的时序特性分析措施：如果坚持用目前的器件，不必理睬该警告。有关进一步的时序特性分析会在后续版本的Quartus得到完善。20.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family因素：用analyze_latches_as_synchronous_elements setting可以让Quaruts II来分析同步锁存，但目前的器件不支持这个特性措施：不必理睬。时序分析也许将锁存器分析成回路。但并不一定分析对的。其后果也许会导致显示提示顾客：变化设计来消除锁 存器21.Warning:Found xx output pins without output pin load capacitance assignment（网友：gucheng82提供）因素：没有给输出管教指定负载电容措施：该功能用于估算TCO和功耗，可以不理睬，也可以在Assignment Editor中为相应的输出管脚指定负载电容，以消除警告22.Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew因素：使用了行波时钟或门控时钟，把触发器的输出当时钟用就会报行波时钟，将组合逻辑的输出当时钟用就会报门控时钟措施：不要把触发器的输出当时钟，不要将组合逻辑的输出当时钟，如果自身如此设计，则不必理睬该警告23.Warning (10268): Verilog HDL information at lcd7106.v(63): Always Construct contains both blocking and non-blocking assignments因素： 一种always模块中同步有阻塞和非阻塞的赋值Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list-没把singal放到process（）中2 Warning: Found pins ing as undefined clocks and/or memory enablesInfo: Assuming node CLK is an undefined clock-=-也许是说设计中产生的触发器没有使能端3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object clk_scan of mode out cannot be read. Change object mode to buffer or inout. -信号类型设立不对，out当作buffer来定义4 Error: Node instance clk_gen1 instantiates undefined entity clk_gen -引用的例化元件未定义实体entity clk_gen5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skewInfo: Detected ripple clock clk_gen:clk_gen1|clk_incr as buffer Info: Detected ripple clock clk_gen:clk_gen1|clk_scan as buffer6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable dataout may not be assigned a new in every possible path through the Process Statement. Signal or variable dataout holds its previous in every path with no new assignment, which may create a combinational loop in the current design.7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal cnt is read inside the Process Statement but isnt in the Process Statements sensivitity list -缺少敏感信号8 Warning: No clock transition on counter_bcd7:counter_counter_clk|q_sig3 register9 Warning: Reduced register counter_bcd7:counter_counter_clk|q_sig3 with stuck clock port to stuck GND10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock class1 with clock skew larger than data delay. See Compilation Report for details.11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock sign with clock skew larger than data delay. See Compilation Report for details.12 Error: VHDL error at counter_clk.vhd(90): actual port class of mode in cannot be associated with formal port class of mode out-两者不能连接起来13 Warning: Ignored node in vector source file. Cant find corresponding node name class_sig2 in design.-没有编写testbench文献，或者没有编辑输入变量的值 testbench里是元件声明和映射14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port class in design entity does not have std_logic_vector type that is specified for the same generic in the associated component -在有关的元件里没有目前文献所定义的类型15 Error: VHDL error at tongbu.vhd(16): cant infer register for signal gate because signal does not hold its outside clock edge16 Warning: Found clock high time violation at 1000.0 ns on register |fcounter|lpm_counter:temp_rtl_0|dffs417 Warning: Compiler packed, optimized or synthesized away node temp19. Ignored vector source file node.-temp19被优化掉了18 Warning: Reduced register gatereg0 with stuck data_in port to stuck GND19 Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin clk Warning: No output dependent on input pin sign-输出信号与输入信号无关，20 Warning: Found clock high time violation at 16625.0 ns on register |impulcomp|gate121 Error: VHDL error at impulcomp.vhd(19): cant implement clock enable condition specified using binary operator or22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter alarm, but formal parameter is not declared-连接表错误，形参alarm赋值给实参，形参没定义，也许是形参与实参的位置颠倒了，规定形参在实参之前。23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors由于前一种错误而导致的错误24 Error: VHDL error at period_counter.vhd(38): type of identifier alarm does not agree with its usage as std_logic typealarm的定义类型与使用的类型不一致warning:Info: Pin num0 not assigned to an exact location on the devicenum0管脚没有在器件上非配一种精确位置解决措施：进行管脚分派。Warning: Found pins functioning as undefined clocks and/or memory enablesInfo: Assuming node clk is an undefined clock因素:是你作为时钟的PIN没有约束信息。可以对相应的PIN做一下设定就行了。重要是指你的某些管脚在电路当中起到了时钟管脚的作用，例如flip-flop的clk管脚，而此管脚没有时钟约束，因此QuartusII把“clk”作为未定义的时钟。措施:如果clk不是时钟，可以加“not clock”的约束；如果是，可以在clock setting当中加入；在某些对时钟规定不很高的状况下，可以忽视此警告或在这里修改:AssignmentsTiming analysis settings.Individualclocks.注旨在Applies to node中只用选择时钟引脚一项即可，required fmax一般比所规定频率高5%即可，不必太紧或太松。25 Error: VHDL error at shift_reg.vhd(24): cant synthesize logic for statement with conditions that test for the edges of multiple clocks -同一进程中具有两个或多种if(edge)条件，（一种进程中之能有一种时钟沿）26 Error: Cant resolve multiple constant drivers for net datain_reg22 at shift_reg.vhd(19)27 cant infer register for signal num0 because signal does not hold its outside clock edge28Error: Cant elaborate top-level user hierarchy29 Error: Cant resolve multiple constant drivers for net cs_in at led_key.vhd(32) -有两个以上赋值语句，不能拟定“cs_in”的值，30 Warning: Ignored node in vector source file. Cant find corresponding node name over in design.-在源文献中找不到相应的节点“over”。31 Error: Cant access JTAG chain 无法找到下载链Warning (10541)的意思是设计中使用了一种未赋值的信号，并且没有复位值，这样该信号为无效值(拟定但不可知)，被其她逻辑使用也许会导致错误。Warning (10036)不用管它，大概是说有个信号未被使用，这样不会对逻辑产生任何影响，固然也可以考虑删除它。Warning (10492)是很常用的，这个关系到编码风格问题。在process里作为被判断信号(if或者case背面的)或者赋值语句右端信号一般应当写在process的敏感信号表里。有些eda工具不检查这个，也许会导致仿真成果与综合出来的电路不一致。事实上，综合工具在综合的时候会自动把此类信号添加到敏感信号表里，但仿真工具不会，而是完全按照代码体现的语意来仿真。Reduced register .这两个应当是阐明eda工具所作的优化，去掉了某些多余的D触发器。Output pins are stuck at VCC or GND 如果正是但愿某些输出被固定置高电平或低电平或者无所谓，就不用管它，否则请检查代码。Design contains 1 input pin(s) that do not drive logic 这个也比较常用，eda工具会提示设计中没被用到的输入，然而这常常就是设计者的本意(不关怀某些输入)。Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew 这就是阐明门控时钟带来的扭曲1.Found clock-sensitive change during active clock edge at time on register 因素：vector source file中时钟敏感信号（如：数据，容许端，清零，同步加载等）在时钟的边沿同步变化。而时钟敏感信号是不能在时钟边沿变化的。其后果为导致成果不对的。措施：编辑vector source file2.Verilog HDL assignment warning at : truncated value with size to match size of target (因素:在HDL设计中对目的的位数进行了设定,如:reg4:0 a;而默觉得32位,将位数裁定到合适的大小措施:如果成果对的,不必加以修正,如果不想看到这个警告,可以变化设定的位数3.All reachable assignments to data_out(10) assign 0, register removed by optimization因素:通过综合器优化后，输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port - changes to this connectivity may change fitting results因素:第9脚，空或接地或接上了电源措施:有时候定义了输出端口，但输出端直接赋0，便会被接地，赋1接电源。如果你的设计中这些端口就是这样用的，那便可以不理睬这些warning5.Found pins functioning as undefined clocks and/or memory enables因素:是你作为时钟的PIN没有约束信息。可以对相应的PIN做一下设定就行了。重要是指你的某些管脚在电路当中起到了时钟管脚的 作用，例如flip-flop的clk管脚，而此管脚没有时钟约束，因此QuartusII把“clk”作为未定义的时钟。措施:如果clk不是时钟，可以加“not clock”的约束；如果是，可以在clock setting当中加入；在某些对时钟规定不很高的状况下，可以忽视此警告或在这里修改:AssignmentsTiming analysis settings.Individual clocks.6.Timing characteristics of device EPM570T144C5 are preliminary因素:由于MAXII 是比較新的元件在 QuartusII 中的時序並不是正式版的,要等 Service Pack措施:只影响 Quartus 的 Waveform7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled措施:将setting中的timing Requirements&Option-More Timing Setting-setting-Enable Clock Latency中的on改成OFF8.Found clock high time violation at 14.8 ns on register |counter|lpm_counter:count1_rtl_0|dffs11因素:违背了steup/hold时间，应当是后仿真，看看波形设立与否和时钟沿符合steup/hold时间措施:在中间加个寄存器也许可以解决问题9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay因素:时钟抖动不小于数据延时,当时钟不久，而if等类的层次过多就会浮现这种问题,但这个问题多是在器件的最高频率中才会浮现措施：setting-timing Requirements&Options-Default required fmax 改小某些，如改到50MHZ10.Design contains input pin(s) that do not drive logic因素:输入引脚没有驱动逻辑(驱动其她引脚）,所有的输入引脚需要有输入逻辑措施:如果这种状况是故意的,不必理睬,如果非故意,输入逻辑驱动.11.Warning：Found clock high time violation at 8.9ns on node TEST3.CLK因素：FF中输入的PLS的保持时间过短措施：在FF中设立较高的时钟频率12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew因素:如果你用的 CPLD 只有一组全局时钟时，用全局时钟分频产生的另一种时钟在布线中当作信号解决，不能保证低的时钟歪斜(SKEW)。会导致在这个时钟上工作的时序电路不可靠，甚至每次布线产生的问题都不同样。措施:如果用有两组以上全局时钟的 FPGA 芯片，可以把第二个全局时钟作为另一种时钟用，可以解决这个问题。第5条补充如下:5.Found pins functioning as undefined clocks and/or memory enables.可以忽视此警告 AssignmentsTiming analysis settings.Individual clocks. new Clock setting-注旨在Applies to node中只用选择时钟引脚一项即可，required fmax一般比所规定频率高5%即可，不必太紧或太松。增长第13条:13.Critical Warning: Timing requirements were not met. See Report window for details.因素：时序规定未满足，措施：双击Compilation Report-Time Analyzer-红色部分（如clock setup:clk等）-左键单击list path,查看fmax的SLACK REPORT再根据提示解决,有也许是程序的算法问题或fmax设立问题ps:人们如果有什么难解决的warning也可以发上来讨论一下,如果有已经解决的疑难warning解决措施,也可以一起分享经验.上面的状况如有错误之处,欢迎拍砖14.Cant achieve minimum setup and hold requirement along path(s). See Report window for details.因素：时序分析发现一定数量的途径违背了最小的建立和保持时间，与时钟歪斜有关,一般是由于多时钟引起的措施：运用Compilation Report-Time Analyzer-红色部分（如clock hold:clk等），在slack中观测是hold time为负值还是setup time 为负值，然后在：Assignment-Assignment Editor-To中增长时钟名(from node finder)，Assignment Name中增长和多时钟有关的Multicycle 和Multicycle Hold选项，如hold time为负，可使Multicycle hold的值multicycle,如设为2和1。15: Cant analyze file - file E:/quartusii/*/*.v is missing因素：试图编译一种不存在的文献，该文献也许被改名或者删除了措施：不管她，没什么影响16.Warning: Cant find signal in vector source file for input pin |whole|clk10m因素：由于你的波形仿真文献（ vector source file ）中并没有把所有的输入信号(input pin)加进去， 对于每一种输入都需要有鼓励源的17.Error: Cant name logic function scfifo0 of instance inst - function has same name as current design file因素：模块的名字和project的名字重名了措施：把两个名字之一改一下，一般改模块的名字1) QuartusII对代码进行时序仿真时浮现Error: Cant continue timing simulation because delay annotation information for design is missing.因素：如果只需要进行功能仿真，不全编译也是可以进行下去的，但时序仿真就必须进行全编译（即工具栏上的紫色实心三角符号那项）。全仿真涉及四个模块：综合器（Synthesis）、电路装配器（Fitter）、组装器（Assember）和时序分析器（Timing Analyzer），任务窗格中会有成功标志（对号）。2) 在下载运营的时候，浮现下面的错误：Warning: The JTAG cable you are using is not supported for Nios II systems. You may experience intermittent JTAG communicationfailures with this cable. Please use a USB Blaster revision B.在运营之前已经将.sof文献下载到开发板上面了，但是仍然浮现上面的问题。解决：在配备的时候，在run之后，进行配备，选择target connection，在最后一项：NIOS II Terminal Communication Device中，要选择none（不要是Jtag_uart）如果采用USB Blaster，可以选择Jtag_uart。之后再run就ok了！3）Error: Cant compile duplicate declarations of entity count3 into library work此错误一般是原理图文献的名字和图中一种器件的名字反复所致，因此更改原理图文献的名字保存即可。-1.Found clock-sensitive change during active clock edge at time on register 因素:vector source file中时钟敏感信号(如:数据,容许端,清零,同步加载等)在时钟的边沿同步变化.而时钟敏感信号是不能在时钟边沿变化的.其后果为导致成果不对的. 措施:编辑vector source file2.Verilog HDL assignment warning at : truncated with size to match size of target ( 因素:在HDL设计中对目的的位数进行了设定,如:reg4:0 a;而默觉得32位, 将位数裁定到合适的大小 措施:如果成果对的,不必加以修正,如果不想看到这个警告,可以变化设定的位数3.All reachable assignments to data_out(10) assign 0, register removed by optimization 因素:通过综合器优化后,输出端口已经不起作用了4.Following 9 pins have nothing, GND, or VCC driving datain port - changes to this connectivity may change fitting results 因素:有9个脚为空或接地或接上了电源 措施:有时候定义了输出端口,但输出端直接赋0,便会被接地,赋1接电源. 如果你的设计中这些端口就是这样用的,那便可以不理睬这些warning5.Found pins functioning as undefined clocks and/or memory enables 因素:是你作为时钟的PIN没有约束信息.可以对相应的PIN做一下设定就行了. 重要是指你的某些管脚在电路当中起到了时钟管脚的作用,例如flip-flop的clk 管脚,而此管脚没有时钟约束,因此QuartusII把“clk”作为未定义的时钟. 措施:如果clk不是时钟,可以加“not clock”的约束;如果是,可以在clock setting当中加入;在某些对时钟规定不很高的状况下,可以忽视此警告或在这里修改:AssignmentsTiming analysis settings.Individual clocks.6.Timing characteristics of device EPM570T144C5 are preliminary因素:由于MAXII 是比較新的元件在 QuartusII 中的時序并不是正式版的,要等 Service Pack措施:只影响 Quartus 的 Waveform7.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled 措施:将setting中的timing Requirements&Option-More Timing Setting-setting-Enable Clock Latency中的on改成OFF8.Found clock high time violation at 14.8 ns on register |counter|lpm_counter:count1_rtl_0|dffs11 因素:违背了steup/hold时间,应当是后仿真,看看波形设立与否和时钟沿符合steup/hold时间 措施:在中间加个寄存器也许可以解决问题9.warning: circuit may not operate.detected 46 non-operational paths clocked by clock clk44 with clock skew larger than data delay 因素:时钟抖动不小于数据延时,当时钟不久,而if等类的层次过多就会浮现这种问 题,但这个问题多是在器件的最高频率中才会浮现 措施:setting-timing Requirements&Options-Default required fmax 改小某些,如改到50MHZ10.Design contains input pin(s) that do not drive logic 因素:输入引脚没有驱动逻辑(驱动其她引脚),所有的输入引脚需要有输入逻辑 措施:如果这种状况是故意的,不必理睬,如果非故意,输入逻辑驱动.11.Warning:Found clock high time violation at 8.9ns on node TEST3.CLK 因素:FF中输入的PLS的保持时间过短 措施:在FF中设立较高的时钟频率12.Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks - node(s) analyzed as buffer(s) resulting in clock skew 因素:如果你用的 CPLD 只有一组全局时钟时,用全局时钟分频产生的另一种时 钟在布线中当作信号解决,不能保证低的时钟歪斜(SKEW).会导致在这个时钟 上工作的时序电路不可靠,甚至每次布线产生的问题都不同样. 措施:如果用有两组以上全局时钟的 FPGA 芯片,可以把第二个全局时钟作为另 一种时钟用,可以解决这个问题.13.Critical Warning: Timing requirements were not met. See Report window for details. 因素:时序规定未满足, 措施:双击Compilation Report-Time Analyzer-红色部分(如clock setup:clk等)-左键单击list path,查看fmax的SLACK REPORT再根据 提示解决,有也许是程序的算法问题14.Cant achieve minimum setup and hold requirement along path(s). See Report window for details. 因素:时序分析发现一定数量的途径违背了最小的建立和保持时间,与时钟歪斜 有关,一般是由于多时钟引起的 措施:运用Compilation Report-Time Analyzer-红色部分(如clock hold:clk等),在slack中观测是hold time为负值还是setup time 为负值, 然后在:Assignment-Assignment Editor-To中增长时钟名(from node finder),Assignment Name中增长 和多时钟有关的Multicycle 和Multicycle Hold选项,如hold time为负,可 使Multicycle hold的值multicycle,如设为2和1.15: Cant analyze file - file E:/quartusii/*/*.v is missing 因素:试图编译一种不存在的文献,该文献也许被改名或者删除了 措施:不管她,没什么影响16.Warning: Cant find signal in vector source file for input pin |whole|clk10m 因素:由于你的波形仿真文献( vector source file )中并没有把所有的输入 信号(input pin)加进去,对于每一种输入都需要有鼓励源的17.Error: Cant name logic scfifo0 of instance inst - has same name as current design file 因素:模块的名字和project的名字重名了 措施:把两个名字之一改一下,一般改模块的名字18.Warning: Using design file lpm_fifo0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: lpm_fifo0 因素:模块不是在本项目生成的,而是直接copy了别的项目的原理图和源程序 而生成的,而不是用QUARTUS将文献添加进本项目 措施:不必理睬,不影响使用19.Timing characteristics of device are preliminary 因素:目前版本的QuartusII只对该器件提供初步的时序特性分析 措施:如果坚持用目前的器件,不必理睬该警告.有关进一步的时序特性分析会在后续版本的Quartus得到完善.20.Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family因素:用analyze_latches_a