VHDL各种D触发器程序

第一题：普通触发器LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;ENTITYDchuISPORT(CLK,D:INSTD_LOGIC;Q:OUTSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(CLK,Q1)BEGINIFCLKEVENTANDCLK二TTHENQ1CLKIIDQENAGLRq第二题：异步清零触发器LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;ENTITYDchuISPORT(CLK,D:INSTD_LOGIC;Q:OUTSTD_LOGIC;ACLK:INSTD_LOGIC);END；ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(ACLK,CLK,Q1)BEGIN”IFACLK=r1rTHENQ1v=9：ELSIFCLKEVENTANDCLK=TTHENQ1=D;ENDIF;ENDPROCESS;Q=Q1;ENDFFQ;CLKACLKf第三题：同步清零触发器LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;ENTITYDchuISPORT(CLK,D:INSTD_LOGIC;Q:OUTSTD_LOGIC;SCLK:INSTD_LOGIC);end；ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESSSCLK,CLK,Q1)BEGINIFCLKEVENTANDCLK屮THEN、IFSCLKTHENQ1v=O；ELSEQ1=D;ENDIF;ENDIF;ENDPROCESS;Q=Q1-ENDFFQ;LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;ENTITYDchuISPORT(CLK:INSTDLOGIC;、D:INSTD_LOGIC;Q;OUTSTD_LOGIC;APRE:INSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(APRE,CLK,Q1)BEGIN.IFAPRE二TTHENQi；ELSIFCLKEVENTANDCLK=TTHENQ1=D;ENDIF;ENDPROCESS;Q=Q1;ENDFFQ;APRE、第五题：同步置位spreLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDchuISPORT(CLK:INSTD_LOGIC；D:INSTD_LOGIGQ;OUTSTD_LOGIC；SPRE:INSTDLOGIC.);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_L0GIC;BEGINPROCESS(SPRE,CLK,Q1)BEGINIFCLKEVENTANDCLQ1THENIFSPRETHENELSEQ1=D;ENDIF;ENDIF;ENDPROCESS;Q=Q1;ENDFFQ;第六题：异步清零，异步置位LIBRARYIEEE;USEIEEE.STD_LOGICJ164.ALL;ENTITYDchuISPORT(CLKACLRAPREDQINSTD_LOGIC;INSTD_LOGIC;INSTD一LOGIC;INSTD_LOGQ;OUTSTD-LOGIC)；END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_L0GIC;BEGINPROCESS(APRE,ACLR,CLK,Q1)BEGIN.IFAGLR=TTHENQ1=V;ELSIFAPRE=*VTHENQ1v=T;ELSIFCLKEVENTANDCLK十THENQ1v=D：ENDIF;ENDPROCESS;QCLFt第七题同步使能LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDchuISPORT(CLK:INSTD_LOGIC*D:INSTD_LOGICj.Q:OUTSTDLOGIC;EN;INSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_L0GIC;BEGINPROCESS(EN,CLK,Q1)BEGINIFCLKEVENTANDCLQTTHENIFEN/THENQ1v=D;ENDIF;ENDIF;ENDPROCESS;Q-cr：,v睞Meo第八题：异步清零，置位，同步使能LIBRARYIEEE;USEIEEE.STD_LOGICJ164.ALL;5ENTITYDchuISPORT(CLKENACLRAPREINSTDLOGIC；INSTD_LOGIC;INSTD_LOGIC;INSTDLOGIC;INSTD_LOGIC;OUTSTDLOGIC)；END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;EGINPROCESS(APRE,ACLR,EN,CLK,Q1)BEGINIFACLR=1rTHENQ1v;ELSIFAPRE=TTHENQ1v=T；ELSIFCLKEVENTANDCLK=TTHENIFEN=TTHENQ1v=D;ENDIF；ENDIF;ENDPROCESS;QAPRiiAcmrAPRiicairfif)嗨DCLKI