keil调试环境下S3C2440.s的分析

页眉内容; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs ; 向量中断模式 / 非向量中断模式设置;通过 PSRs（程序状态寄存器）来设置; 系统工作模式设定; CPSR是当系统前程序状态寄存器， SPSR是备份程序状态寄存器。其中 CPSR共用一个物理寄存器，而 SPSR一共有 5 个物理寄存器; CPSR寄存器设定： CPSR4.0 为 M4-M0 ，通过它可以设定处理器的工作模式Mode_USREQU0x10 ; 用户模式Mode_FIQEQU0x11 ; 快速中断模式Mode_IRQEQU0x12 ; 外部中断模式Mode_SVCEQU0x13 ; 超级用户模式Mode_ABTEQU0x17 ; 数据访问终止模式Mode_UNDEQU0x1B ; 未定义指令终止模式Mode_SYSEQU0x1F ; 系统模式I_BitEQU0x80; when I bit is set, IRQ is disabled外部中断屏蔽位， 置 1，关闭中断， 置 0，打开中断F_BitEQU0x40; when F bit is set, FIQ is disabled快速中断屏蔽位，置 1，关闭中断，置0，打开中断;- Stack and Heap Definitions -;/ Stack Configuration (Stack Sizes in Bytes);/ Undefined Mode;/ Supervisor Mode;/ Abort Mode;/ Fast Interrupt Mode ;/ Interrupt Mode;/ User/System Mode;/ ; 栈配置，系统的栈空间设定UND_Stack_Size EQU0x00000000 ; 未定义模式的栈大小SVC_Stack_Size EQU0x00000008 ; 超级用户模式的栈大小ABT_Stack_Size EQU0x00000000 ; 数据访问终止模式的栈大小FIQ_Stack_Size EQU0x00000000 ; 快速中断模式的栈大小IRQ_Stack_Size EQU0x00000080 ; 外部中断模式的栈大小USR_Stack_Size EQU0x00000400 ; 用户模式的栈大小ISR_Stack_Size EQU(UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size) 所;有模式的堆栈相加得到总堆栈的大小; ARM 的汇编程序由段组成，段是相对独立的指令或数据单位，每个段由AREA 伪指令定义，并定义段的属性。-READWRITE（读写）、READONLY（只读）AREASTACK, NOINIT, READWRITE, ALIGN=3开;辟一个堆栈段， 段名字为 STACK，定义为可读可写，; 不初始化内存单元，或将内存单元初始化为0Stack_MemSPACEUSR_Stack_Size ;_initial_spSPACEISR_Stack_Size ; 汇编代码的地址标号Stack_Top ; 堆栈段内容结束，在这里放个标号 ,用来获得堆栈顶部地址;/ Heap Configuration;/Heap Size (in Bytes) 页眉内容;/ Heap_SizeEQU0x00000000 ; 堆大小设置AREAHEAP, NOINIT, READWRITE, ALIGN=3 开;辟一个段，名字为HEAP可读可写，不初始化内存单元，或者初始化为0_heap_baseHeap_MemSPACEHeap_Size_heap_limit;-Memory Definitions -; Internal Memory Base Addresses ;片上 SRAM 的基地址，即内存基地址IRAM_BASEEQU0x;-Watchdog Timer Definitions -WT_BASEEQU0x; Watchdog Timer Base Address 看门狗定时器基地址WTCON_OFSEQU0x00; Watchdog TimerControl Register Offset 看门狗控制寄存器偏移地址，相对于基址WTDAT_OFSEQU0x04; Watchdog TimerData RegisterOffset 看门狗数据寄存器偏移地址，相对于基址WTCNT_OFSEQU0x08; Watchdog TimerCount RegisterOffset 看门狗计数寄存器偏移地址，相对于基址;/ Watchdog Timer Setup;/ Watchdog Timer Control Register (WTCON);/Prescaler Value ;/Watchdog Timer Enable;/Clock Division Factor;/ 16 32 64 128;/Interrupt Generation Enable;/Reset Enable;/;/ Watchdog Timer Data Register (WTDAT);/Count Reload Value ;/;/ Watchdog Timer SetupWT_SETUPEQU1 ; 看门狗设置WTCON_ValEQU0x00000000 ;看门狗控制寄存器设置，关闭看门狗WTDAT_ValEQU0x00008000 ; 看门狗数据寄存器设置，初始值即为0x8000;-Clock and Power Management Definitions -CLOCK_BASEEQU0x4C000000; Clock Base Address ; 时钟基地址LOCKTIME_OFSEQU0x00; PLL Lock Time Count RegisterOffset ; 锁相环锁定时间计数寄存器偏移地址，相对于基址MPLLCON_OFSEQU0x04; MPLL Configuration RegisterOffset ; MPLL 配置寄存器偏移地址，相对于基址，主时钟源 PLLUPLLCON_OFSEQU0x08; UPLL Configuration RegisterOffset ; UPLL配置寄存器偏移地址，相对于基址， USB时钟源 PLLCLKCON_OFSEQU0x0C; Clock Generator Control RegOffset ; 时钟控制寄存器偏移地址，相对于基址页眉内容CLKSLOW_OFSEQU0x10; Clock Slow Control RegisterOffset; 时钟减慢控制寄存器偏移地址，相对于基址CLKDIVN_OFSEQU0x14; Clock Divider Control Register Offset ;时钟分频器控制寄存器偏移地址，相对于基址CAMDIVN_OFSEQU0x18; Camera Clock Divider RegisterOffset ; 摄像头时钟分频器控制寄存器偏移地址，相对于基址，UPLL提供;/ Clock Setup;/ PLL Lock Time Count Register (LOCKTIME);/ U_LTIME: UPLL Lock Time Count Value for UCLK ;/ M_LTIME: MPLL Lock Time Count Value for FCLK, HCLK and PCLK ;/;/ MPLL Configuration Register (MPLLCON);/ MPLL = (2 * m * Fin) / (p * 2s);/ m: Main Divider m Value ;/ m = MDIV + 8;/p: Pre-divider p Value ;/ p = PDIV + 2;/s: Post Divider s Value ;/ s = SDIV;/;/ UPLL Configuration Register (UPLLCON);/ UPLL = ( m * Fin) / (p * 2s);/ m: Main Divider m Value ;/ m = MDIV + 8;/p: Pre-divider p Value ;/ p = PDIV + 2;/s: Post Divider s Value ;/ s = SDIV;/;/ Clock Generation Control Register (CLKCON);/AC97 Enable;/Camera Enable;/SPI Enable;/IIS Enable;/IIC Enable;/ADC + Touch Screen Enable;/RTC Enable;/GPIO Enable;/UART2 Enable;/UART1 Enable;/UART0 Enable;/SDI Enable;/PWMTIMER Enable;/USB Device Enable页眉内容;/USB Host Enable;/LCDC Enable;/NAND FLASH Controller Enable;/SLEEP Enable;/IDLE BIT Enable;/;/ Clock Slow Control Register (CLKSLOW);/UCLK_ON: UCLK ON;/MPLL_OFF: Turn off PLL;/SLOW_BIT: Slow Mode Enable;/SLOW_VAL: Slow Clock Divider ;/;/ Clock Divider Control Register (CLKDIVN);/DIVN_UPLL: UCLK Select;/ UCLK = UPLL clock;/ UCLK = UPLL clock / 2;/HDIVN: HCLK Select;/ HCLK = FCLK;/ HCLK = FCLK / 2;/ HCLK = FCLK / 4 if HCLK4_HALF = 0 in CAMDIVN, else HCLK = FCLK / 8;/ HCLK = FCLK / 3 if HCLK3_HALF = 0 in CAMDIVN, else HCLK = FCLK / 6;/PDIVN: PCLK Select;/ PCLK = HCLK;/ PCLK = HCLK / 2;/;/ Camera Clock Divider Control Register (CAMDIVN);/DVS_EN: ARM Core Clock Select;/ ARM core runs at FCLK;/ ARM core runs at HCLK;/HCLK4_HALF: HDIVN Division Rate Change Bit;/ If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 4;/ If HDIVN = 2 in CLKDIVN then HCLK = FCLK / 8;/HCLK3_HALF: HDIVN Division Rate Change Bit;/ If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 3;/ If HDIVN = 3 in CLKDIVN then HCLK = FCLK / 6;/CAMCLK Select;/ CAMCLK = UPLL;/ CAMCLK = UPLL / CAMCLK_DIV;/CAMCLK_DIV: CAMCLK Divider ;/ Camera Clock = UPLL / (2 * (CAMCLK_DIV + 1);/ Divider is used only if CAMCLK_SEL = 1;/;/ Clock SetupCLOCK_SETUPEQU0 ; 时钟设置页眉内容LOCKTIME_ValEQU0x0FFF0FFF ; PLL锁定时间计数器值MPLLCON_ValEQU0x00043011 ; MPLL 配置寄存器值UPLLCON_ValEQU0x00038021 ; UPLL 配置寄存器值CLKCON_ValEQU0x001FFFF0 ; 时钟配置寄存器值CLKSLOW_ValEQU0x00000004 ; 时钟减慢控制寄存器值CLKDIVN_ValEQU0x0000000F ; 时钟分频控制寄存器值CAMDIVN_ValEQU0x00000000 ; 摄像头分频控制寄存器值;-Memory Controller Definitions -; 存储控制器设置MC_BASEEQU0x; Memory Controller Base Address ; 存储控制器基地址BWSCON_OFSEQU0x00; Bus Width and Wait Status Ctrl Offset ; 总线宽度和等待控制寄存器BANKCON0_OFSEQU0x04; Bank 0 Control RegisterOffset ; BANK0-BOOT ROM控制寄存器设置BANKCON1_OFSEQU0x08; Bank 1 Control RegisterOffset ; BANK1BANKCON2_OFSEQU0x0C; Bank 2 Control RegisterOffset ; BANK2BANKCON3_OFSEQU0x10; Bank 3 Control RegisterOffset ; BANK3BANKCON4_OFSEQU0x14; Bank 4 Control RegisterOffset ; BANK4BANKCON5_OFSEQU0x18; Bank 5 Control RegisterOffset ; BANK5BANKCON6_OFSEQU0x1C; Bank 6 Control RegisterOffset ; BANK6BANKCON7_OFSEQU0x20; Bank 7 Control RegisterOffset ; BANK7REFRESH_OFSEQU0x24; SDRAM Refresh Control Register Offset ; DRAM/SDRAM刷新控制BANKSIZE_OFSEQU0x28; Flexible Bank Size RegisterOffset ; 可调的 bank 大小寄存器MRSRB6_OFSEQU0x2C; Bank 6 Mode RegisterOffset ;模式控制寄存器bank6MRSRB7_OFSEQU0x30; Bank 7 Mode RegisterOffset ;模式控制寄存器bank7;/ Memory Controller Setup;/ Bus Width and Wait Control Register (BWSCON);/ST7: Use UB/LB for Bank 7;/WS7: Enable Wait Status for Bank 7;/ DW7: Data Bus Width for Bank 7;/ 8-bit 16-bit 32-bit Reserved;/ST6: Use UB/LB for Bank 6;/WS6: Enable Wait Status for Bank 6;/ DW6: Data Bus Width for Bank 6;/ 8-bit 16-bit 32-bit Reserved;/ST5: Use UB/LB for Bank 5;/WS5: Enable Wait Status for Bank 5;/ DW5: Data Bus Width for Bank 5;/ 8-bit 16-bit 32-bit Reserved;/ST4: Use UB/LB for Bank 4;/WS4: Enable Wait Status for Bank 4;/ DW4: Data Bus Width for Bank 4;/ 8-bit 16-bit 32-bit Reserved;/ST3: Use UB/LB for Bank 3;/WS3: Enable Wait Status for Bank 3页眉内容;/ DW3: Data Bus Width for Bank 3;/ 8-bit 16-bit 32-bit Reserved;/ST2: Use UB/LB for Bank 2;/WS2: Enable Wait Status for Bank 2;/DW2: Data Bus Width for Bank 2;/ 8-bit 16-bit 32-bit Reserved;/ST1: Use UB/LB for Bank 1;/WS1: Enable Wait Status for Bank 1;/DW1: Data Bus Width for Bank 1;/ 8-bit 16-bit 32-bit Reserved;/DW0: Indicate Data Bus Width for Bank 0;/ 16-bit 32-bit;/;/ Bank 0 Control Register (BANKCON0);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacc: Access Cycle;/1 clocks2 clocks3 clocks4 clocks;/6 clocks8 clocks 10 clocks 14 clocks;/Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacp: Page Mode Access Cycle at Page Mode;/ 2 clocks 3 clocks 4 clocks 6 clocks;/PMC: Page Mode Configuration;/ normal (1 data) 4 data 8 data 16 data;/;/ Bank 1 Control Register (BANKCON1);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacc: Access Cycle;/1 clocks2 clocks3 clocks4 clocks;/6 clocks8 clocks 10 clocks 14 clocks;/Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacp: Page Mode Access Cycle at Page Mode;/ 2 clocks 3 clocks 4 clocks 6 clocks页眉内容;/PMC: Page Mode Configuration;/ normal (1 data) 4 data 8 data 16 data;/;/ Bank 2 Control Register (BANKCON2);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacc: Access Cycle;/1 clocks2 clocks3 clocks4 clocks;/6 clocks8 clocks 10 clocks 14 clocks;/Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacp: Page Mode Access Cycle at Page Mode;/ 2 clocks 3 clocks 4 clocks 6 clocks;/PMC: Page Mode Configuration;/ normal (1 data) 4 data 8 data 16 data;/;/ Bank 3 Control Register (BANKCON3);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacc: Access Cycle;/1 clocks2 clocks3 clocks4 clocks;/6 clocks8 clocks 10 clocks 14 clocks;/Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacp: Page Mode Access Cycle at Page Mode;/ 2 clocks 3 clocks 4 clocks 6 clocks;/PMC: Page Mode Configuration;/ normal (1 data) 4 data 8 data 16 data;/;/ Bank 4 Control Register (BANKCON4);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacc: Access Cycle;/1 clocks2 clocks3 clocks4 clocks页眉内容;/6 clocks8 clocks 10 clocks 14 clocks;/Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacp: Page Mode Access Cycle at Page Mode;/ 2 clocks 3 clocks 4 clocks 6 clocks;/PMC: Page Mode Configuration;/ normal (1 data) 4 data 8 data 16 data;/;/ Bank 5 Control Register (BANKCON5);/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacc: Access Cycle;/1 clocks2 clocks3 clocks4 clocks;/6 clocks8 clocks 10 clocks 14 clocks;/Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacp: Page Mode Access Cycle at Page Mode;/ 2 clocks 3 clocks 4 clocks 6 clocks;/PMC: Page Mode Configuration;/ normal (1 data) 4 data 8 data 16 data;/;/ Bank 6 Control Register (BANKCON6);/ Memory Type Selection;/ ROM or SRAM SDRAM;/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacc: Access Cycle;/1 clocks2 clocks3 clocks4 clocks;/6 clocks8 clocks 10 clocks 14 clocks;/Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay;/Parameter depends on Memory Type: if type SRAM then parameter is Tacp,;/if type is SDRAM then parameter is Trcd页眉内容;/For SDRAM 6 cycles setting is not allowed;/ 2 clocks 3 clocks 4 clocks 6 clocks;/PMC/SCAN: Page Mode Configuration / Column Address Number ;/Parameter depends on Memory Type: if type SRAM then parameter is PMC,;/if type is SDRAM then parameter is SCAN;/;/ Bank 7 Control Register (BANKCON7);/ Memory Type Selection;/ ROM or SRAM SDRAM;/ Tacs: Address Set-up Time before nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/ Tcos: Chip Selection Set-up Time before nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacc: Access Cycle;/1 clocks2 clocks 3 clocks 4 clocks;/6 clocks8 clocks 10 clocks 14 clocks;/Tcoh: Chip Selection Hold Time after nOE;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tcah: Address Hold Time after nGCS;/ 0 clocks 1 clocks 2 clocks 4 clocks;/Tacp/Trcd: Page Mode Access Cycle at Page Mode / RAS to CAS Delay;/Parameter depends on Memory Type: if type SRAM then parameter is Tacp,;/if type is SDRAM then parameter is Trcd;/For SDRAM 6 cycles setting is not allowed;/ 2 clocks 3 clocks 4 clocks 6 clocks;/PMC/SCAN: Page Mode Configuration / Column